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Update llvm code gen tests to assume v3.8 syntax
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benl23x5 committed May 3, 2016
1 parent 32034f3 commit 88ec625
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Showing 2 changed files with 21 additions and 21 deletions.
4 changes: 2 additions & 2 deletions test/ddc-main/20-CoreSalt/32-ToLLVM/Test.stdout.check
Original file line number Diff line number Diff line change
Expand Up @@ -90,8 +90,8 @@ l20.entry:



!16 = metadata !{metadata !"ptr_r", metadata !15, i32 0}
!15 = metadata !{metadata !"ptr_ROOT_14", null, i32 1}
!16 = !{!"ptr_r", !15, i32 0}
!15 = !{!"ptr_ROOT_14", null, i32 1}



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38 changes: 19 additions & 19 deletions test/ddc-main/20-CoreSalt/33-ToLLVM-MD/Test.stdout.check
Original file line number Diff line number Diff line change
Expand Up @@ -21,11 +21,11 @@ l9.entry:
%_v10.xval1.addr1 = ptrtoint i64* %_v1.x to i64
%_v10.xval1.addr2 = add i64 %_v10.xval1.addr1, 0
%_v10.xval1.ptr = inttoptr i64 %_v10.xval1.addr2 to i64*
%_v10.xval1 = load i64* %_v10.xval1.ptr, !tbaa !7
%_v10.xval1 = load i64, i64* %_v10.xval1.ptr, !tbaa !7
%_v11.yval1.addr1 = ptrtoint i64* %_v2.y to i64
%_v11.yval1.addr2 = add i64 %_v11.yval1.addr1, 0
%_v11.yval1.ptr = inttoptr i64 %_v11.yval1.addr2 to i64*
%_v11.yval1 = load i64* %_v11.yval1.ptr, !tbaa !6
%_v11.yval1 = load i64, i64* %_v11.yval1.ptr, !tbaa !6
%_v12.a = add i64 %_v10.xval1, %_v11.yval1
%_v13.addr1 = ptrtoint i64* %_v3.z to i64
%_v14.addr2 = add i64 %_v13.addr1, 0
Expand All @@ -34,22 +34,22 @@ l9.entry:
%_v16.xval2.addr1 = ptrtoint i64* %_v1.x to i64
%_v16.xval2.addr2 = add i64 %_v16.xval2.addr1, 0
%_v16.xval2.ptr = inttoptr i64 %_v16.xval2.addr2 to i64*
%_v16.xval2 = load i64* %_v16.xval2.ptr, !tbaa !7
%_v16.xval2 = load i64, i64* %_v16.xval2.ptr, !tbaa !7
%_v17.yval2.addr1 = ptrtoint i64* %_v2.y to i64
%_v17.yval2.addr2 = add i64 %_v17.yval2.addr1, 0
%_v17.yval2.ptr = inttoptr i64 %_v17.yval2.addr2 to i64*
%_v17.yval2 = load i64* %_v17.yval2.ptr, !tbaa !6
%_v17.yval2 = load i64, i64* %_v17.yval2.ptr, !tbaa !6
%_v18.b = add i64 %_v16.xval2, %_v17.yval2
%_v19 = mul i64 %_v12.a, %_v18.b
ret i64 %_v19
}



!8 = metadata !{metadata !"x_plus_y_square_rz", metadata !5, i32 0}
!7 = metadata !{metadata !"x_plus_y_square_rx", metadata !6, i32 0}
!6 = metadata !{metadata !"x_plus_y_square_ry", metadata !5, i32 0}
!5 = metadata !{metadata !"x_plus_y_square_ROOT_4", null, i32 1}
!8 = !{!"x_plus_y_square_rz", !5, i32 0}
!7 = !{!"x_plus_y_square_rx", !6, i32 0}
!6 = !{!"x_plus_y_square_ry", !5, i32 0}
!5 = !{!"x_plus_y_square_ROOT_4", null, i32 1}


-- Observable optimisations: GVN - constprop behaviour
Expand All @@ -72,24 +72,24 @@ l11.entry:
%_v12.a.addr1 = ptrtoint i64* %_v7.x to i64
%_v12.a.addr2 = add i64 %_v12.a.addr1, 0
%_v12.a.ptr = inttoptr i64 %_v12.a.addr2 to i64*
%_v12.a = load i64* %_v12.a.ptr, !tbaa !10
%_v12.a = load i64, i64* %_v12.a.ptr, !tbaa !10
%_v13.b = add i64 %_v12.a, 1
%_v15._d14 = call fastcc i64 @nothing (i64* %_v7.x)
%_v16.c.addr1 = ptrtoint i64* %_v7.x to i64
%_v16.c.addr2 = add i64 %_v16.c.addr1, 0
%_v16.c.ptr = inttoptr i64 %_v16.c.addr2 to i64*
%_v16.c = load i64* %_v16.c.ptr, !tbaa !10
%_v16.c = load i64, i64* %_v16.c.ptr, !tbaa !10
%_v17.d = mul i64 %_v16.c, 2
%_v18 = add i64 %_v13.b, %_v17.d
ret i64 %_v18
}



!4 = metadata !{metadata !"nothing_rx", metadata !3, i32 0}
!3 = metadata !{metadata !"nothing_ROOT_2", null, i32 1}
!10 = metadata !{metadata !"three_x_plus_one_rx", metadata !9, i32 1}
!9 = metadata !{metadata !"three_x_plus_one_ROOT_8", null, i32 1}
!4 = !{!"nothing_rx", !3, i32 0}
!3 = !{!"nothing_ROOT_2", null, i32 1}
!10 = !{!"three_x_plus_one_rx", !9, i32 1}
!9 = !{!"three_x_plus_one_ROOT_8", null, i32 1}


-- Observarble optimisations: LICM
Expand All @@ -110,7 +110,7 @@ l13.default:
%_v14.yval.addr1 = ptrtoint i64* %_v3.y to i64
%_v14.yval.addr2 = add i64 %_v14.yval.addr1, 0
%_v14.yval.ptr = inttoptr i64 %_v14.yval.addr2 to i64*
%_v14.yval = load i64* %_v14.yval.ptr, !tbaa !9
%_v14.yval = load i64, i64* %_v14.yval.ptr, !tbaa !9
%_v15.yplustwo = add i64 %_v14.yval, 2
%_v16.addr1 = ptrtoint i64* %_v2.x to i64
%_v17.addr2 = add i64 %_v16.addr1, 0
Expand All @@ -127,10 +127,10 @@ l13.default:



!9 = metadata !{metadata !"go_ry", metadata !6, i32 0}
!8 = metadata !{metadata !"go_rx", metadata !6, i32 0}
!7 = metadata !{metadata !"go_ra", metadata !6, i32 0}
!6 = metadata !{metadata !"go_ROOT_5", null, i32 1}
!9 = !{!"go_ry", !6, i32 0}
!8 = !{!"go_rx", !6, i32 0}
!7 = !{!"go_ra", !6, i32 0}
!6 = !{!"go_ROOT_5", null, i32 1}



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