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From @hqueue on May 16, 2017 11:47
For ARM32, double register number is not shown correctly in JitDump, JitDisasm and etc.
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An example from coreclr unit test.
$ COMPlus_JitDisasm=DblAdd COMPlus_JitDump=DblAdd ./corerun tests/JIT/CodeGenBringUpTests/DblAdd/DblAdd.exe ...(omitted)... IN0001: 000006 EE30 0B01 vadd d0, d0, d2 ...(omitted)... IN0001: 000006 vadd d0, d0, d2However above instruction encoding means
vadd d0, d0, d1. -
Another example from recent PR for ryujit/arm32.
I was confused with below example ([RyuJIT/ARM32] Enable casting from small int to float coreclr#11643 (comment)) in the PR.IN0074: 000180 EEB8 4BC4 vcvt.i2d d8, s8This means
vcvt.i2d d4, s8, i.e. single-float register number is correct, but double register number is incorrectly displayed.
Both LegacyJIT and RyuJIT have same problem.
Copied from original issue: dotnet/coreclr#11646
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