resolve merge comflict

dotnet · Dec 17, 2024 · 0eef560 · 0eef560
1 parent a9a3d5c
commit 0eef560
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Showing 2 changed files with 4 additions and 13 deletions.
diff --git a/src/coreclr/jit/compiler.cpp b/src/coreclr/jit/compiler.cpp
@@ -2299,13 +2299,6 @@ void Compiler::compSetProcessor()
         if (canUseApxEncoding())
         {
             codeGen->GetEmitter()->SetUseRex2Encoding(true);
-        }
-        if (canUseApxEncodings())
-        {
-            // TODO-Xarch-apx:
-            //   At this stage, since no machine will pass the CPUID check for APX, we need a special stress mode that 
-            //   enables REX2 on incompatible platform, `DoJitStressRex2Encoding` is expected to be removed eventually.
-            codeGen->GetEmitter()->SetUseRex2Encoding(true);
             codeGen->GetEmitter()->SetUsePromotedEVEXEncoding(true);
         }
     }

diff --git a/src/coreclr/jit/emitxarch.cpp b/src/coreclr/jit/emitxarch.cpp
@@ -14830,7 +14830,7 @@ BYTE* emitter::emitOutputSV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
             case EA_1BYTE:
 #ifdef TARGET_AMD64
                 assert((ins != INS_lzcnt_evex) && (ins != INS_tzcnt_evex) && (ins != INS_popcnt_evex));
-#endif TARGET_AMD64
+#endif // TARGET_AMD64
                 break;
 
             case EA_2BYTE:
@@ -14846,10 +14846,9 @@ BYTE* emitter::emitOutputSV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
             case EA_4BYTE:
                 code |= 0x01;
                 break;
+
 #ifdef TARGET_AMD64
             case EA_8BYTE:
-#endif // TARGET_AMD64
-
                 /* Set the 'w' size bit to indicate 32-bit operation
                  * Note that incrementing "code" for INS_call (0xFF) would
                  * overflow, whereas setting the lower bit to 1 just works out
@@ -14860,15 +14859,14 @@ BYTE* emitter::emitOutputSV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
                         assert(hasEvexPrefix(code));
                         code = AddRexWPrefix(id, code);
                     }
-#ifdef TARGET_AMD64
                     if ((ins != INS_lzcnt_evex) && (ins != INS_tzcnt_evex) && (ins != INS_popcnt_evex))
                     // These instructions do not support 1-byte inputs and the opcode is exact.
-#endif // TARGET_AMD64
                     {
-                    code |= 0x01;
+                        code |= 0x01;
                     }     
                     break;
                 }
+#endif //TARGET_AMD64
 
 #ifdef TARGET_X86
             case EA_8BYTE: