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Prevent new codepaths for X86
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@khushal1996
khushal1996 committed Mar 8, 2024
1 parent d47fd37 commit 2367f40
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Showing 4 changed files with 69 additions and 46 deletions.
4 changes: 2 additions & 2 deletions src/coreclr/jit/compiler.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3172,7 +3172,7 @@ class Compiler
GenTree* op3,
CorInfoType simdBaseJitType,
unsigned simdSize);
#if defined(TARGET_AMD64)
GenTree* gtNewSimdCvtNode(var_types type,
GenTree* op1,
NamedIntrinsic hwIntrinsicID,
Expand All @@ -3184,7 +3184,7 @@ class Compiler
var_types sourceType,
var_types targetType,
unsigned simdSize);

#endif //TARGET_AMD64
GenTree* gtNewSimdCreateBroadcastNode(
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize);

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37 changes: 20 additions & 17 deletions src/coreclr/jit/gentree.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -21251,9 +21251,8 @@ GenTree* Compiler::gtNewSimdCeilNode(var_types type, GenTree* op1, CorInfoType s
return gtNewSimdHWIntrinsicNode(type, op1, intrinsic, simdBaseJitType, simdSize);
}

#if defined(TARGET_XARCH)
GenTreeVecCon* Compiler::gtCvtCtrlTbl
(var_types type, var_types sourceType, var_types targetType, unsigned simdSize)
#if defined(TARGET_AMD64)
GenTreeVecCon* Compiler::gtCvtCtrlTbl(var_types type, var_types sourceType, var_types targetType, unsigned simdSize)
{
assert(IsBaselineSimdIsaSupportedDebugOnly());
assert(IsBaselineVector512IsaSupportedDebugOnly());
Expand All @@ -21262,7 +21261,6 @@ GenTreeVecCon* Compiler::gtCvtCtrlTbl
assert(varTypeIsSIMD(type));
assert(getSIMDTypeForSize(simdSize) == type);


GenTreeVecCon* tbl = gtNewVconNode(type);

switch (sourceType)
Expand All @@ -21277,20 +21275,20 @@ GenTreeVecCon* Compiler::gtCvtCtrlTbl
tbl->gtSimdVal.i64[i] = 0x08080088;
}
break;

case TYP_INT:
case TYP_LONG:
for (int i = 0; i < 8; i++)
{
tbl->gtSimdVal.i64[i] = 0x00000088;
}
break;

default:
unreached();
}
break;

case TYP_FLOAT:
switch (targetType)
{
Expand All @@ -21301,28 +21299,32 @@ GenTreeVecCon* Compiler::gtCvtCtrlTbl
tbl->gtSimdVal.i32[i] = 0x08080088;
}
break;

case TYP_INT:
case TYP_LONG:
for (int i = 0; i < 16; i++)
{
tbl->gtSimdVal.i32[i] = 0x00000088;
}
break;

default:
unreached();
}
break;

default:
unreached();
}
return tbl;
}

GenTree* Compiler::gtNewSimdCvtNode
(var_types type, GenTree* op1, NamedIntrinsic hwIntrinsicID, CorInfoType simdTargetBaseJitType, CorInfoType simdSourceBaseJitType, unsigned simdSize)
GenTree* Compiler::gtNewSimdCvtNode(var_types type,
GenTree* op1,
NamedIntrinsic hwIntrinsicID,
CorInfoType simdTargetBaseJitType,
CorInfoType simdSourceBaseJitType,
unsigned simdSize)
{
assert(IsBaselineSimdIsaSupportedDebugOnly());
assert(IsBaselineVector512IsaSupportedDebugOnly());
Expand All @@ -21343,17 +21345,18 @@ GenTree* Compiler::gtNewSimdCvtNode
GenTree* op1Clone = fgMakeMultiUse(&op1);

// run vfixupimmsd base on table and no flags reporting
GenTree* fixupVal = gtNewSimdHWIntrinsicNode(type, op1, op1Clone, tbl, gtNewIconNode(0),
NI_AVX512F_Fixup, simdSourceBaseJitType, simdSize);
GenTree* fixupVal = gtNewSimdHWIntrinsicNode(type, op1, op1Clone, tbl, gtNewIconNode(0), NI_AVX512F_Fixup,
simdSourceBaseJitType, simdSize);

if (varTypeIsSigned(simdTargetBaseType))
{
ssize_t actualMaxVal = (varTypeIsInt(simdTargetBaseType)) ? INT32_MAX : INT64_MAX;

GenTree* maxVal = gtNewDconNode(static_cast<double>(actualMaxVal), simdSourceBaseType);

maxVal = gtNewSimdCreateBroadcastNode(type, maxVal, simdSourceBaseJitType, simdSize);
GenTree* maxValDup = gtNewSimdCreateBroadcastNode(type, gtNewIconNode(actualMaxVal, simdTargetBaseType), simdTargetBaseJitType, simdSize);
maxVal = gtNewSimdCreateBroadcastNode(type, maxVal, simdSourceBaseJitType, simdSize);
GenTree* maxValDup = gtNewSimdCreateBroadcastNode(type, gtNewIconNode(actualMaxVal, simdTargetBaseType),
simdTargetBaseJitType, simdSize);

// we will be using the input value twice
GenTree* fixupValDup = fgMakeMultiUse(&fixupVal);
Expand All @@ -21372,7 +21375,7 @@ GenTree* Compiler::gtNewSimdCvtNode
return gtNewSimdHWIntrinsicNode(type, fixupVal, hwIntrinsicID, simdSourceBaseJitType, simdSize);
}
}
#endif //TARGET_XARCH
#endif // TARGET_AMD64

GenTree* Compiler::gtNewSimdCmpOpNode(
genTreeOps op, var_types type, GenTree* op1, GenTree* op2, CorInfoType simdBaseJitType, unsigned simdSize)
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34 changes: 21 additions & 13 deletions src/coreclr/jit/hwintrinsicxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1446,16 +1446,18 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_DOUBLE);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
op1 = impSIMDPopStack();

intrinsic = (simdSize == 16) ? NI_AVX512DQ_VL_ConvertToVector128Int64WithTruncation
: (simdSize == 32) ? NI_AVX512DQ_VL_ConvertToVector256Int64WithTruncation
: NI_AVX512DQ_ConvertToVector512Int64WithTruncation;
: (simdSize == 32) ? NI_AVX512DQ_VL_ConvertToVector256Int64WithTruncation
: NI_AVX512DQ_ConvertToVector512Int64WithTruncation;

retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_LONG, simdBaseJitType, simdSize);
}
#endif
break;
}

Expand All @@ -1465,15 +1467,17 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_FLOAT);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
op1 = impSIMDPopStack();
op1 = impSIMDPopStack();
intrinsic = (simdSize == 16) ? NI_AVX512F_VL_ConvertToVector128UInt32WithTruncation
: (simdSize == 32) ? NI_AVX512F_VL_ConvertToVector256UInt32WithTruncation
: NI_AVX512F_ConvertToVector512UInt32WithTruncation;
: (simdSize == 32) ? NI_AVX512F_VL_ConvertToVector256UInt32WithTruncation
: NI_AVX512F_ConvertToVector512UInt32WithTruncation;

retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_UINT, simdBaseJitType, simdSize);
}
#endif
break;
}

Expand All @@ -1483,15 +1487,17 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_DOUBLE);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
op1 = impSIMDPopStack();
op1 = impSIMDPopStack();
intrinsic = (simdSize == 16) ? NI_AVX512DQ_VL_ConvertToVector128UInt64WithTruncation
: (simdSize == 32) ? NI_AVX512DQ_VL_ConvertToVector256UInt64WithTruncation
: NI_AVX512DQ_ConvertToVector512UInt64WithTruncation;
: (simdSize == 32) ? NI_AVX512DQ_VL_ConvertToVector256UInt64WithTruncation
: NI_AVX512DQ_ConvertToVector512UInt64WithTruncation;

retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_ULONG, simdBaseJitType, simdSize);
}
#endif
break;
}

Expand All @@ -1501,15 +1507,17 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_FLOAT);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
op1 = impSIMDPopStack();
op1 = impSIMDPopStack();
intrinsic = (simdSize == 16) ? NI_SSE2_ConvertToVector128Int32WithTruncation
: (simdSize == 32) ? NI_AVX_ConvertToVector256Int32WithTruncation
: NI_AVX512F_ConvertToVector512Int32WithTruncation;
: (simdSize == 32) ? NI_AVX_ConvertToVector256Int32WithTruncation
: NI_AVX512F_ConvertToVector512Int32WithTruncation;

retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_INT, simdBaseJitType, simdSize);
}
#endif
break;
}

Expand Down Expand Up @@ -1538,8 +1546,8 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
else if (simdBaseType == TYP_UINT && IsBaselineVector512IsaSupportedOpportunistically())
{
intrinsic = (simdSize == 16) ? NI_AVX512F_VL_ConvertToVector128Single
: (simdSize == 32) ? NI_AVX512F_VL_ConvertToVector256Single
: NI_AVX512F_ConvertToVector512Single;
: (simdSize == 32) ? NI_AVX512F_VL_ConvertToVector256Single
: NI_AVX512F_ConvertToVector512Single;
}
if (intrinsic != NI_Illegal)
{
Expand Down
40 changes: 26 additions & 14 deletions src/coreclr/jit/simdashwintrinsic.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -532,12 +532,12 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,
case NI_VectorT_ConvertToUInt32:
case NI_VectorT_ConvertToUInt64:
{
#ifdef TARGET_XARCH
#ifdef TARGET_AMD64
if (IsBaselineVector512IsaSupportedOpportunistically())
{
break;
}
#endif // TARGET_XARCH
#endif // TARGET_AMD64
return nullptr;
}

Expand Down Expand Up @@ -1181,58 +1181,70 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_DOUBLE);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
NamedIntrinsic intrinsic = (simdSize == 16) ? NI_AVX512DQ_VL_ConvertToVector128Int64WithTruncation
: (simdSize == 32) ? NI_AVX512DQ_VL_ConvertToVector256Int64WithTruncation
: NI_AVX512DQ_ConvertToVector512Int64WithTruncation;
NamedIntrinsic intrinsic =
(simdSize == 16) ? NI_AVX512DQ_VL_ConvertToVector128Int64WithTruncation
: (simdSize == 32) ? NI_AVX512DQ_VL_ConvertToVector256Int64WithTruncation
: NI_AVX512DQ_ConvertToVector512Int64WithTruncation;

return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_LONG, simdBaseJitType, simdSize);
}
#endif
return nullptr;
}

case NI_VectorT_ConvertToUInt32:
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_FLOAT);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
NamedIntrinsic intrinsic = (simdSize == 16) ? NI_AVX512F_VL_ConvertToVector128UInt32WithTruncation
: (simdSize == 32) ? NI_AVX512F_VL_ConvertToVector256UInt32WithTruncation
: NI_AVX512F_ConvertToVector512UInt32WithTruncation;
NamedIntrinsic intrinsic =
(simdSize == 16) ? NI_AVX512F_VL_ConvertToVector128UInt32WithTruncation
: (simdSize == 32) ? NI_AVX512F_VL_ConvertToVector256UInt32WithTruncation
: NI_AVX512F_ConvertToVector512UInt32WithTruncation;

return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_UINT, simdBaseJitType, simdSize);
}
#endif
return nullptr;
}

case NI_VectorT_ConvertToUInt64:
{
assert(sig->numArgs == 1);
assert(simdBaseType == TYP_DOUBLE);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
NamedIntrinsic intrinsic = (simdSize == 16) ? NI_AVX512DQ_VL_ConvertToVector128UInt64WithTruncation
: (simdSize == 32) ? NI_AVX512DQ_VL_ConvertToVector256UInt64WithTruncation
: NI_AVX512DQ_ConvertToVector512UInt64WithTruncation;
NamedIntrinsic intrinsic =
(simdSize == 16) ? NI_AVX512DQ_VL_ConvertToVector128UInt64WithTruncation
: (simdSize == 32) ? NI_AVX512DQ_VL_ConvertToVector256UInt64WithTruncation
: NI_AVX512DQ_ConvertToVector512UInt64WithTruncation;

return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_ULONG, simdBaseJitType, simdSize);
}
#endif
return nullptr;
}

case NI_VectorT_ConvertToInt32:
{
assert(simdBaseType == TYP_FLOAT);
#if defined(TARGET_AMD64)
if (IsBaselineVector512IsaSupportedOpportunistically())
{
NamedIntrinsic intrinsic = (simdSize == 16) ? NI_SSE2_ConvertToVector128Int32WithTruncation
: (simdSize == 32) ? NI_AVX_ConvertToVector256Int32WithTruncation
: NI_AVX512F_ConvertToVector512Int32WithTruncation;
NamedIntrinsic intrinsic =
(simdSize == 16) ? NI_SSE2_ConvertToVector128Int32WithTruncation
: (simdSize == 32) ? NI_AVX_ConvertToVector256Int32WithTruncation
: NI_AVX512F_ConvertToVector512Int32WithTruncation;

return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_INT, simdBaseJitType, simdSize);
}
#endif
return nullptr;
}

Expand Down

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