Arm64: Add xtn and xtn2 intrinsics codegen, api and tests.

dotnet · Apr 2, 2020 · 323a277 · 323a277
1 parent 372bf42
commit 323a277
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Showing 24 changed files with 6,478 additions and 2 deletions.
diff --git a/src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp b/src/coreclr/src/jit/hwintrinsiccodegenarm64.cpp
@@ -293,6 +293,14 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
                 GetEmitter()->emitIns_R_R_R(ins, emitSize, targetReg, op2Reg, op1Reg, opt);
                 break;
 
+            case NI_AdvSimd_ExtractAndNarrowHigh:
+                if (targetReg != op1Reg)
+                {
+                    GetEmitter()->emitIns_R_R(INS_mov, emitSize, targetReg, op1Reg);
+                }
+                GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op2Reg, opt);
+                break;
+
             case NI_AdvSimd_FusedMultiplyAddScalar:
             case NI_AdvSimd_FusedMultiplyAddNegatedScalar:
             case NI_AdvSimd_FusedMultiplySubtractNegatedScalar:

diff --git a/src/coreclr/src/jit/hwintrinsiclistarm64.h b/src/coreclr/src/jit/hwintrinsiclistarm64.h
@@ -69,6 +69,8 @@ HARDWARE_INTRINSIC(AdvSimd,         CompareLessThan,                           -
 HARDWARE_INTRINSIC(AdvSimd,         CompareLessThanOrEqual,                    -1,              -1,           2,     {INS_cmge,              INS_cmhs,           INS_cmge,           INS_cmhs,           INS_cmge,           INS_cmhs,           INS_invalid,        INS_invalid,        INS_fcmge,          INS_invalid},           HW_Category_SimpleSIMD,             HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize|HW_Flag_SpecialCodeGen)
 HARDWARE_INTRINSIC(AdvSimd,         CompareTest,                               -1,              -1,           2,     {INS_cmtst,             INS_cmtst,          INS_cmtst,          INS_cmtst,          INS_cmtst,          INS_cmtst,          INS_invalid,        INS_invalid,        INS_cmtst,          INS_invalid},           HW_Category_SimpleSIMD,             HW_Flag_NoContainment|HW_Flag_Commutative|HW_Flag_UnfixedSIMDSize)
 HARDWARE_INTRINSIC(AdvSimd,         DivideScalar,                              -1,               8,           2,     {INS_invalid,           INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_fdiv,           INS_fdiv},              HW_Category_SIMDScalar,             HW_Flag_NoContainment)
+HARDWARE_INTRINSIC(AdvSimd,         ExtractAndNarrowLow,                       -1,               8,           1,     {INS_xtn,               INS_xtn,            INS_xtn,            INS_xtn,            INS_xtn,            INS_xtn,            INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid},           HW_Category_SimpleSIMD,             HW_Flag_NoContainment)
+HARDWARE_INTRINSIC(AdvSimd,         ExtractAndNarrowHigh,                      -1,              16,           2,     {INS_xtn2,              INS_xtn2,           INS_xtn2,           INS_xtn2,           INS_xtn2,           INS_xtn2,           INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid},           HW_Category_SimpleSIMD,             HW_Flag_NoContainment|HW_Flag_SpecialCodeGen)
 HARDWARE_INTRINSIC(AdvSimd,         FusedMultiplyAdd,                          -1,              -1,           3,     {INS_invalid,           INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_fmla,           INS_invalid},           HW_Category_SimpleSIMD,             HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
 HARDWARE_INTRINSIC(AdvSimd,         FusedMultiplyAddScalar,                    -1,               8,           3,     {INS_invalid,           INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_fmadd,          INS_fmadd},             HW_Category_SIMDScalar,             HW_Flag_NoContainment|HW_Flag_SpecialCodeGen)
 HARDWARE_INTRINSIC(AdvSimd,         FusedMultiplyAddNegatedScalar,             -1,               8,           3,     {INS_invalid,           INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_invalid,        INS_fnmadd,         INS_fnmadd},            HW_Category_SIMDScalar,             HW_Flag_NoContainment|HW_Flag_SpecialCodeGen)

diff --git a/src/coreclr/src/jit/lsraarm64.cpp b/src/coreclr/src/jit/lsraarm64.cpp
@@ -1150,6 +1150,17 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree)
                 srcCount += BuildDelayFreeUses(op3);
                 break;
 
+            case NI_AdvSimd_ExtractAndNarrowHigh:
+
+                assert((numArgs == 2) && (op2 != nullptr));
+
+                buildUses = false;
+
+                tgtPrefUse = BuildUse(op1);
+                srcCount += 1;
+                srcCount += BuildDelayFreeUses(op2);
+                break;
+
             default:
                 assert((intrinsicId > NI_HW_INTRINSIC_START) && (intrinsicId < NI_HW_INTRINSIC_END));
                 break;

diff --git a/src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_r.csproj b/src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_r.csproj
@@ -225,6 +225,18 @@
     <Compile Include="CompareTest.Vector128.UInt32.cs" />
     <Compile Include="DivideScalar.Vector64.Double.cs" />
     <Compile Include="DivideScalar.Vector64.Single.cs" />
+    <Compile Include="ExtractAndNarrowLow.Vector128.Int16.cs" />
+    <Compile Include="ExtractAndNarrowLow.Vector128.Int32.cs" />
+    <Compile Include="ExtractAndNarrowLow.Vector128.Int64.cs" />
+    <Compile Include="ExtractAndNarrowLow.Vector128.UInt16.cs" />
+    <Compile Include="ExtractAndNarrowLow.Vector128.UInt32.cs" />
+    <Compile Include="ExtractAndNarrowLow.Vector128.UInt64.cs" />
+    <Compile Include="ExtractAndNarrowHigh.Vector128.Int16.cs" />
+    <Compile Include="ExtractAndNarrowHigh.Vector128.Int32.cs" />
+    <Compile Include="ExtractAndNarrowHigh.Vector128.Int64.cs" />
+    <Compile Include="ExtractAndNarrowHigh.Vector128.UInt16.cs" />
+    <Compile Include="ExtractAndNarrowHigh.Vector128.UInt32.cs" />
+    <Compile Include="ExtractAndNarrowHigh.Vector128.UInt64.cs" />
     <Compile Include="FusedMultiplyAdd.Vector64.Single.cs" />
     <Compile Include="FusedMultiplyAdd.Vector128.Single.cs" />
     <Compile Include="FusedMultiplyAddScalar.Vector64.Double.cs" />

diff --git a/src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_ro.csproj b/src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_ro.csproj
@@ -225,6 +225,18 @@
     <Compile Include="CompareTest.Vector128.UInt32.cs" />
     <Compile Include="DivideScalar.Vector64.Double.cs" />
     <Compile Include="DivideScalar.Vector64.Single.cs" />
+    <Compile Include="ExtractAndNarrowLow.Vector128.Int16.cs" />
+    <Compile Include="ExtractAndNarrowLow.Vector128.Int32.cs" />
+    <Compile Include="ExtractAndNarrowLow.Vector128.Int64.cs" />
+    <Compile Include="ExtractAndNarrowLow.Vector128.UInt16.cs" />
+    <Compile Include="ExtractAndNarrowLow.Vector128.UInt32.cs" />
+    <Compile Include="ExtractAndNarrowLow.Vector128.UInt64.cs" />
+    <Compile Include="ExtractAndNarrowHigh.Vector128.Int16.cs" />
+    <Compile Include="ExtractAndNarrowHigh.Vector128.Int32.cs" />
+    <Compile Include="ExtractAndNarrowHigh.Vector128.Int64.cs" />
+    <Compile Include="ExtractAndNarrowHigh.Vector128.UInt16.cs" />
+    <Compile Include="ExtractAndNarrowHigh.Vector128.UInt32.cs" />
+    <Compile Include="ExtractAndNarrowHigh.Vector128.UInt64.cs" />
     <Compile Include="FusedMultiplyAdd.Vector64.Single.cs" />
     <Compile Include="FusedMultiplyAdd.Vector128.Single.cs" />
     <Compile Include="FusedMultiplyAddScalar.Vector64.Double.cs" />