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[runtime] Arm64: Add ZipLow, ZipHigh, UnzipOdd and UnzipEven codegen …
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…and tests. (#1190)
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@TamarChristinaArm @echesakov
TamarChristinaArm authored and echesakov committed Jan 3, 2020
1 parent 5e2c61b commit 662817d
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Showing 76 changed files with 36,593 additions and 3 deletions.
36 changes: 36 additions & 0 deletions src/coreclr/src/jit/codegenarm64.cpp
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Expand Up @@ -7042,6 +7042,42 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R(INS_uminlv, EA_8BYTE, REG_V12, REG_V13, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_uminlv, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_4S);

// uzp1 vector
theEmitter->emitIns_R_R(INS_uzp1, EA_8BYTE, REG_V4, REG_V5, INS_OPTS_8B);
theEmitter->emitIns_R_R(INS_uzp1, EA_16BYTE, REG_V6, REG_V7, INS_OPTS_16B);
theEmitter->emitIns_R_R(INS_uzp1, EA_8BYTE, REG_V8, REG_V9, INS_OPTS_4H);
theEmitter->emitIns_R_R(INS_uzp1, EA_16BYTE, REG_V10, REG_V11, INS_OPTS_8H);
theEmitter->emitIns_R_R(INS_uzp1, EA_8BYTE, REG_V12, REG_V13, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_uzp1, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_uzp1, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_2D);

// uzp2 vector
theEmitter->emitIns_R_R(INS_uzp2, EA_8BYTE, REG_V4, REG_V5, INS_OPTS_8B);
theEmitter->emitIns_R_R(INS_uzp2, EA_16BYTE, REG_V6, REG_V7, INS_OPTS_16B);
theEmitter->emitIns_R_R(INS_uzp2, EA_8BYTE, REG_V8, REG_V9, INS_OPTS_4H);
theEmitter->emitIns_R_R(INS_uzp2, EA_16BYTE, REG_V10, REG_V11, INS_OPTS_8H);
theEmitter->emitIns_R_R(INS_uzp2, EA_8BYTE, REG_V12, REG_V13, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_uzp2, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_uzp2, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_2D);

// zip1 vector
theEmitter->emitIns_R_R(INS_zip1, EA_8BYTE, REG_V4, REG_V5, INS_OPTS_8B);
theEmitter->emitIns_R_R(INS_zip1, EA_16BYTE, REG_V6, REG_V7, INS_OPTS_16B);
theEmitter->emitIns_R_R(INS_zip1, EA_8BYTE, REG_V8, REG_V9, INS_OPTS_4H);
theEmitter->emitIns_R_R(INS_zip1, EA_16BYTE, REG_V10, REG_V11, INS_OPTS_8H);
theEmitter->emitIns_R_R(INS_zip1, EA_8BYTE, REG_V12, REG_V13, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_zip1, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_zip1, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_2D);

// zip2 vector
theEmitter->emitIns_R_R(INS_zip2, EA_8BYTE, REG_V4, REG_V5, INS_OPTS_8B);
theEmitter->emitIns_R_R(INS_zip2, EA_16BYTE, REG_V6, REG_V7, INS_OPTS_16B);
theEmitter->emitIns_R_R(INS_zip2, EA_8BYTE, REG_V8, REG_V9, INS_OPTS_4H);
theEmitter->emitIns_R_R(INS_zip2, EA_16BYTE, REG_V10, REG_V11, INS_OPTS_8H);
theEmitter->emitIns_R_R(INS_zip2, EA_8BYTE, REG_V12, REG_V13, INS_OPTS_2S);
theEmitter->emitIns_R_R(INS_zip2, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_4S);
theEmitter->emitIns_R_R(INS_zip2, EA_16BYTE, REG_V14, REG_V15, INS_OPTS_2D);

// faddp scalar
theEmitter->emitIns_R_R(INS_faddp, EA_4BYTE, REG_V0, REG_V1);
theEmitter->emitIns_R_R(INS_faddp, EA_8BYTE, REG_V2, REG_V3);
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12 changes: 11 additions & 1 deletion src/coreclr/src/jit/emitarm64.cpp
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Expand Up @@ -5304,6 +5304,13 @@ void emitter::emitIns_R_R_R(
case INS_uabd:
case INS_umax:
case INS_umin:
assert(elemsize != EA_8BYTE); // can't use 2D or 1D
__fallthrough;

case INS_uzp1:
case INS_uzp2:
case INS_zip1:
case INS_zip2:
assert(isVectorRegister(reg1));
assert(isVectorRegister(reg2));
assert(isVectorRegister(reg3));
Expand All @@ -5313,7 +5320,6 @@ void emitter::emitIns_R_R_R(
assert(isValidVectorDatasize(size));
assert(isValidArrangement(size, opt));
elemsize = optGetElemsize(opt);
assert(elemsize != EA_8BYTE); // can't use 2D or 1D

fmt = IF_DV_3A;
break;
Expand Down Expand Up @@ -12892,6 +12898,10 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
case INS_umax:
case INS_smin:
case INS_smax:
case INS_uzp1:
case INS_uzp2:
case INS_zip1:
case INS_zip2:
result.insThroughput = PERFSCORE_THROUGHPUT_2X;
result.insLatency = PERFSCORE_LATENCY_2C;
break;
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4 changes: 4 additions & 0 deletions src/coreclr/src/jit/hwintrinsiclistarm64.h
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Expand Up @@ -89,6 +89,10 @@ HARDWARE_INTRINSIC(AdvSimd_Arm64, CompareLessThan, -
HARDWARE_INTRINSIC(AdvSimd_Arm64, CompareLessThanOrEqual, -1, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_cmge, INS_cmhs, INS_invalid, INS_fcmge}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_SpecialCodeGen)
HARDWARE_INTRINSIC(AdvSimd_Arm64, CompareTest, -1, 16, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_cmtst, INS_cmtst, INS_invalid, INS_cmtst}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_Commutative)
HARDWARE_INTRINSIC(AdvSimd_Arm64, ReverseElementBits, -1, -1, 1, {INS_rbit, INS_rbit, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd_Arm64, UnzipEven, -1, -1, 2, {INS_uzp1, INS_uzp1, INS_uzp1, INS_uzp1, INS_uzp1, INS_uzp1, INS_uzp1, INS_uzp1, INS_uzp1, INS_uzp1}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd_Arm64, UnzipOdd, -1, -1, 2, {INS_uzp2, INS_uzp2, INS_uzp2, INS_uzp2, INS_uzp2, INS_uzp2, INS_uzp2, INS_uzp2, INS_uzp2, INS_uzp2}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd_Arm64, ZipHigh, -1, -1, 2, {INS_zip2, INS_zip2, INS_zip2, INS_zip2, INS_zip2, INS_zip2, INS_zip2, INS_zip2, INS_zip2, INS_zip2}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)
HARDWARE_INTRINSIC(AdvSimd_Arm64, ZipLow, -1, -1, 2, {INS_zip1, INS_zip1, INS_zip1, INS_zip1, INS_zip1, INS_zip1, INS_zip1, INS_zip1, INS_zip1, INS_zip1}, HW_Category_SimpleSIMD, HW_Flag_NoContainment|HW_Flag_UnfixedSIMDSize)

// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
// ISA Function name ival SIMD size NumArg instructions Category Flags
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12 changes: 12 additions & 0 deletions src/coreclr/src/jit/instrsarm64.h
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Expand Up @@ -1221,6 +1221,18 @@ INST1(umaxv, "umaxv", 0, 0, IF_DV_2M, 0x2E30A800)
INST1(uminv, "uminv", 0, 0, IF_DV_2M, 0x2E31A800)
// uminv Vd,Vn DV_2M 0Q101110XX110001 101010nnnnnddddd 2E31 A800 Vd,Vn (vector)

INST1(uzp1, "uzp1", 0, 0, IF_DV_3A, 0x0E001800)
// uzp1 Vd,Vn,Vm DV_3A 0Q001110XX0mmmmm 000110nnnnnddddd 0E00 1800 Vd,Vn,Vm (vector)

INST1(uzp2, "uzp2", 0, 0, IF_DV_3A, 0x0E005800)
// upz2 Vd,Vn,Vm DV_3A 0Q001110XX0mmmmm 010110nnnnnddddd 0E00 5800 Vd,Vn,Vm (vector)

INST1(zip1, "zip1", 0, 0, IF_DV_3A, 0x0E003800)
// zip1 Vd,Vn,Vm DV_3A 0Q001110XX0mmmmm 011110nnnnnddddd 0E00 3800 Vd,Vn,Vm (vector)

INST1(zip2, "zip2", 0, 0, IF_DV_3A, 0x0E007800)
// zip2 Vd,Vn,Vm DV_3A 0Q001110XX0mmmmm 001110nnnnnddddd 0E00 7800 Vd,Vn,Vm (vector)

INST1(xtn, "xtn", 0, 0, IF_DV_2M, 0x0E212800)
// xtn Vd,Vn DV_2M 00101110XX110000 001110nnnnnddddd 0E21 2800 Vd,Vn (vector)

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68 changes: 68 additions & 0 deletions src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_r.csproj
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Expand Up @@ -46,6 +46,74 @@
<Compile Include="ReverseElementBits.Vector128.SByte.cs" />
<Compile Include="ReverseElementBits.Vector64.Byte.cs" />
<Compile Include="ReverseElementBits.Vector64.SByte.cs" />
<Compile Include="UnzipEven.Vector64.Byte.cs" />
<Compile Include="UnzipEven.Vector64.Int16.cs" />
<Compile Include="UnzipEven.Vector64.Int32.cs" />
<Compile Include="UnzipEven.Vector64.SByte.cs" />
<Compile Include="UnzipEven.Vector64.Single.cs" />
<Compile Include="UnzipEven.Vector64.UInt16.cs" />
<Compile Include="UnzipEven.Vector64.UInt32.cs" />
<Compile Include="UnzipEven.Vector128.Byte.cs" />
<Compile Include="UnzipEven.Vector128.Double.cs" />
<Compile Include="UnzipEven.Vector128.Int16.cs" />
<Compile Include="UnzipEven.Vector128.Int32.cs" />
<Compile Include="UnzipEven.Vector128.Int64.cs" />
<Compile Include="UnzipEven.Vector128.SByte.cs" />
<Compile Include="UnzipEven.Vector128.Single.cs" />
<Compile Include="UnzipEven.Vector128.UInt16.cs" />
<Compile Include="UnzipEven.Vector128.UInt32.cs" />
<Compile Include="UnzipEven.Vector128.UInt64.cs" />
<Compile Include="UnzipOdd.Vector64.Byte.cs" />
<Compile Include="UnzipOdd.Vector64.Int16.cs" />
<Compile Include="UnzipOdd.Vector64.Int32.cs" />
<Compile Include="UnzipOdd.Vector64.SByte.cs" />
<Compile Include="UnzipOdd.Vector64.Single.cs" />
<Compile Include="UnzipOdd.Vector64.UInt16.cs" />
<Compile Include="UnzipOdd.Vector64.UInt32.cs" />
<Compile Include="UnzipOdd.Vector128.Byte.cs" />
<Compile Include="UnzipOdd.Vector128.Double.cs" />
<Compile Include="UnzipOdd.Vector128.Int16.cs" />
<Compile Include="UnzipOdd.Vector128.Int32.cs" />
<Compile Include="UnzipOdd.Vector128.Int64.cs" />
<Compile Include="UnzipOdd.Vector128.SByte.cs" />
<Compile Include="UnzipOdd.Vector128.Single.cs" />
<Compile Include="UnzipOdd.Vector128.UInt16.cs" />
<Compile Include="UnzipOdd.Vector128.UInt32.cs" />
<Compile Include="UnzipOdd.Vector128.UInt64.cs" />
<Compile Include="ZipLow.Vector64.Byte.cs" />
<Compile Include="ZipLow.Vector64.Int16.cs" />
<Compile Include="ZipLow.Vector64.Int32.cs" />
<Compile Include="ZipLow.Vector64.SByte.cs" />
<Compile Include="ZipLow.Vector64.Single.cs" />
<Compile Include="ZipLow.Vector64.UInt16.cs" />
<Compile Include="ZipLow.Vector64.UInt32.cs" />
<Compile Include="ZipLow.Vector128.Byte.cs" />
<Compile Include="ZipLow.Vector128.Double.cs" />
<Compile Include="ZipLow.Vector128.Int16.cs" />
<Compile Include="ZipLow.Vector128.Int32.cs" />
<Compile Include="ZipLow.Vector128.Int64.cs" />
<Compile Include="ZipLow.Vector128.SByte.cs" />
<Compile Include="ZipLow.Vector128.Single.cs" />
<Compile Include="ZipLow.Vector128.UInt16.cs" />
<Compile Include="ZipLow.Vector128.UInt32.cs" />
<Compile Include="ZipLow.Vector128.UInt64.cs" />
<Compile Include="ZipHigh.Vector64.Byte.cs" />
<Compile Include="ZipHigh.Vector64.Int16.cs" />
<Compile Include="ZipHigh.Vector64.Int32.cs" />
<Compile Include="ZipHigh.Vector64.SByte.cs" />
<Compile Include="ZipHigh.Vector64.Single.cs" />
<Compile Include="ZipHigh.Vector64.UInt16.cs" />
<Compile Include="ZipHigh.Vector64.UInt32.cs" />
<Compile Include="ZipHigh.Vector128.Byte.cs" />
<Compile Include="ZipHigh.Vector128.Double.cs" />
<Compile Include="ZipHigh.Vector128.Int16.cs" />
<Compile Include="ZipHigh.Vector128.Int32.cs" />
<Compile Include="ZipHigh.Vector128.Int64.cs" />
<Compile Include="ZipHigh.Vector128.SByte.cs" />
<Compile Include="ZipHigh.Vector128.Single.cs" />
<Compile Include="ZipHigh.Vector128.UInt16.cs" />
<Compile Include="ZipHigh.Vector128.UInt32.cs" />
<Compile Include="ZipHigh.Vector128.UInt64.cs" />
<Compile Include="Program.AdvSimd.Arm64.cs" />
<Compile Include="..\Shared\Helpers.cs" />
<Compile Include="..\Shared\Program.cs" />
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68 changes: 68 additions & 0 deletions src/coreclr/tests/src/JIT/HardwareIntrinsics/Arm/AdvSimd.Arm64/AdvSimd.Arm64_ro.csproj
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Expand Up @@ -46,6 +46,74 @@
<Compile Include="ReverseElementBits.Vector128.SByte.cs" />
<Compile Include="ReverseElementBits.Vector64.Byte.cs" />
<Compile Include="ReverseElementBits.Vector64.SByte.cs" />
<Compile Include="UnzipEven.Vector64.Byte.cs" />
<Compile Include="UnzipEven.Vector64.Int16.cs" />
<Compile Include="UnzipEven.Vector64.Int32.cs" />
<Compile Include="UnzipEven.Vector64.SByte.cs" />
<Compile Include="UnzipEven.Vector64.Single.cs" />
<Compile Include="UnzipEven.Vector64.UInt16.cs" />
<Compile Include="UnzipEven.Vector64.UInt32.cs" />
<Compile Include="UnzipEven.Vector128.Byte.cs" />
<Compile Include="UnzipEven.Vector128.Double.cs" />
<Compile Include="UnzipEven.Vector128.Int16.cs" />
<Compile Include="UnzipEven.Vector128.Int32.cs" />
<Compile Include="UnzipEven.Vector128.Int64.cs" />
<Compile Include="UnzipEven.Vector128.SByte.cs" />
<Compile Include="UnzipEven.Vector128.Single.cs" />
<Compile Include="UnzipEven.Vector128.UInt16.cs" />
<Compile Include="UnzipEven.Vector128.UInt32.cs" />
<Compile Include="UnzipEven.Vector128.UInt64.cs" />
<Compile Include="UnzipOdd.Vector64.Byte.cs" />
<Compile Include="UnzipOdd.Vector64.Int16.cs" />
<Compile Include="UnzipOdd.Vector64.Int32.cs" />
<Compile Include="UnzipOdd.Vector64.SByte.cs" />
<Compile Include="UnzipOdd.Vector64.Single.cs" />
<Compile Include="UnzipOdd.Vector64.UInt16.cs" />
<Compile Include="UnzipOdd.Vector64.UInt32.cs" />
<Compile Include="UnzipOdd.Vector128.Byte.cs" />
<Compile Include="UnzipOdd.Vector128.Double.cs" />
<Compile Include="UnzipOdd.Vector128.Int16.cs" />
<Compile Include="UnzipOdd.Vector128.Int32.cs" />
<Compile Include="UnzipOdd.Vector128.Int64.cs" />
<Compile Include="UnzipOdd.Vector128.SByte.cs" />
<Compile Include="UnzipOdd.Vector128.Single.cs" />
<Compile Include="UnzipOdd.Vector128.UInt16.cs" />
<Compile Include="UnzipOdd.Vector128.UInt32.cs" />
<Compile Include="UnzipOdd.Vector128.UInt64.cs" />
<Compile Include="ZipLow.Vector64.Byte.cs" />
<Compile Include="ZipLow.Vector64.Int16.cs" />
<Compile Include="ZipLow.Vector64.Int32.cs" />
<Compile Include="ZipLow.Vector64.SByte.cs" />
<Compile Include="ZipLow.Vector64.Single.cs" />
<Compile Include="ZipLow.Vector64.UInt16.cs" />
<Compile Include="ZipLow.Vector64.UInt32.cs" />
<Compile Include="ZipLow.Vector128.Byte.cs" />
<Compile Include="ZipLow.Vector128.Double.cs" />
<Compile Include="ZipLow.Vector128.Int16.cs" />
<Compile Include="ZipLow.Vector128.Int32.cs" />
<Compile Include="ZipLow.Vector128.Int64.cs" />
<Compile Include="ZipLow.Vector128.SByte.cs" />
<Compile Include="ZipLow.Vector128.Single.cs" />
<Compile Include="ZipLow.Vector128.UInt16.cs" />
<Compile Include="ZipLow.Vector128.UInt32.cs" />
<Compile Include="ZipLow.Vector128.UInt64.cs" />
<Compile Include="ZipHigh.Vector64.Byte.cs" />
<Compile Include="ZipHigh.Vector64.Int16.cs" />
<Compile Include="ZipHigh.Vector64.Int32.cs" />
<Compile Include="ZipHigh.Vector64.SByte.cs" />
<Compile Include="ZipHigh.Vector64.Single.cs" />
<Compile Include="ZipHigh.Vector64.UInt16.cs" />
<Compile Include="ZipHigh.Vector64.UInt32.cs" />
<Compile Include="ZipHigh.Vector128.Byte.cs" />
<Compile Include="ZipHigh.Vector128.Double.cs" />
<Compile Include="ZipHigh.Vector128.Int16.cs" />
<Compile Include="ZipHigh.Vector128.Int32.cs" />
<Compile Include="ZipHigh.Vector128.Int64.cs" />
<Compile Include="ZipHigh.Vector128.SByte.cs" />
<Compile Include="ZipHigh.Vector128.Single.cs" />
<Compile Include="ZipHigh.Vector128.UInt16.cs" />
<Compile Include="ZipHigh.Vector128.UInt32.cs" />
<Compile Include="ZipHigh.Vector128.UInt64.cs" />
<Compile Include="Program.AdvSimd.Arm64.cs" />
<Compile Include="..\Shared\Helpers.cs" />
<Compile Include="..\Shared\Program.cs" />
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