Skip to content

Commit

Permalink
[mono] Add Vector128 Negate and OnesComplement intrinsics for amd64 (#…
Browse files Browse the repository at this point in the history 
…74993)

* Vector128 Negate intrinsics (two's complement)

* AMD64 OnesComplement intrinsics for Vector128/64

* Negate + OnesComplement operands,fix missing break

* Simplify OP_AMD64_NEGATION


* Conditional Select for amd64, refactor arm64 code

* Re-use Arm64 code for Negate and OnesComplement

* rename ones complement

* Update src/mono/mono/mini/mini-ops.h remove space

Co-authored-by: Fan Yang <52458914+fanyang-mono@users.noreply.github.com>

* remove space mini-ops.hs

* remove blank line

Co-authored-by: Fan Yang <52458914+fanyang-mono@users.noreply.github.com>
  • Loading branch information
@matouskozak @fanyang-mono
matouskozak and fanyang-mono authored Sep 30, 2022
1 parent 3ea12ef commit 9bc025d
Show file tree
Hide file tree
Showing 3 changed files with 34 additions and 40 deletions.
52 changes: 24 additions & 28 deletions src/mono/mono/mini/mini-llvm.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9958,14 +9958,6 @@ MONO_RESTORE_WARNING
values [ins->dreg] = immediate_unroll_end (&ictx, &cbb);
break;
}
case OP_ARM64_MVN: {
LLVMTypeRef ret_t = LLVMTypeOf (lhs);
LLVMValueRef result = bitcast_to_integral (ctx, lhs);
result = LLVMBuildNot (builder, result, "arm64_mvn");
result = convert (ctx, result, ret_t);
values [ins->dreg] = result;
break;
}
case OP_ARM64_BIC: {
LLVMTypeRef ret_t = LLVMTypeOf (lhs);
LLVMValueRef result = bitcast_to_integral (ctx, lhs);
Expand Down Expand Up @@ -10527,25 +10519,6 @@ MONO_RESTORE_WARNING
values [ins->dreg] = result;
break;
}
case OP_ARM64_XNEG:
case OP_ARM64_XNEG_SCALAR: {
gboolean scalar = ins->opcode == OP_ARM64_XNEG_SCALAR;
gboolean is_float = FALSE;
switch (inst_c1_type (ins)) {
case MONO_TYPE_R4: case MONO_TYPE_R8: is_float = TRUE;
}
LLVMValueRef result = lhs;
if (scalar)
result = scalar_from_vector (ctx, result);
if (is_float)
result = LLVMBuildFNeg (builder, result, "arm64_xneg");
else
result = LLVMBuildNeg (builder, result, "arm64_xneg");
if (scalar)
result = vector_from_scalar (ctx, LLVMTypeOf (lhs), result);
values [ins->dreg] = result;
break;
}
case OP_ARM64_PMULL:
case OP_ARM64_PMULL2: {
gboolean high = ins->opcode == OP_ARM64_PMULL2;
Expand Down Expand Up @@ -11302,9 +11275,32 @@ MONO_RESTORE_WARNING
values [ins->dreg] = result;
break;
}
case OP_NEGATION:
case OP_NEGATION_SCALAR: {
gboolean scalar = ins->opcode == OP_NEGATION_SCALAR;
gboolean is_float = (ins->inst_c1 == MONO_TYPE_R4 || ins->inst_c1 == MONO_TYPE_R8);

LLVMValueRef result = lhs;
if (scalar)
result = scalar_from_vector (ctx, result);
if (is_float)
result = LLVMBuildFNeg (builder, result, "");
else
result = LLVMBuildNeg (builder, result, "");
if (scalar)
result = vector_from_scalar (ctx, LLVMTypeOf (lhs), result);
values [ins->dreg] = result;
break;
}
case OP_ONES_COMPLEMENT: {
LLVMTypeRef ret_t = LLVMTypeOf (lhs);
LLVMValueRef result = bitcast_to_integral (ctx, lhs);
result = LLVMBuildNot (builder, result, "");
result = convert (ctx, result, ret_t);
values [ins->dreg] = result;
break;
}
#endif

case OP_DUMMY_USE:
break;

Expand Down
10 changes: 4 additions & 6 deletions src/mono/mono/mini/mini-ops.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1627,9 +1627,6 @@ MINI_OP(OP_ARM64_REVN, "arm64_revn", XREG, XREG, NONE)
MINI_OP(OP_ARM64_PMULL, "arm64_pmull", XREG, XREG, XREG)
MINI_OP(OP_ARM64_PMULL2, "arm64_pmull2", XREG, XREG, XREG)

MINI_OP(OP_ARM64_XNEG, "arm64_xneg", XREG, XREG, NONE)
MINI_OP(OP_ARM64_XNEG_SCALAR, "arm64_xneg_scalar", XREG, XREG, NONE)

MINI_OP(OP_ARM64_SMULL, "arm64_smull", XREG, XREG, XREG)
MINI_OP(OP_ARM64_SMULL_SCALAR, "arm64_smull_scalar", XREG, XREG, XREG)
MINI_OP(OP_ARM64_SMULL2, "arm64_smull2", XREG, XREG, XREG)
Expand Down Expand Up @@ -1721,8 +1718,6 @@ MINI_OP(OP_ARM64_CMTST, "arm64_cmtst", XREG, XREG, XREG)

MINI_OP(OP_ARM64_BIC, "arm64_bic", XREG, XREG, XREG)

MINI_OP(OP_ARM64_MVN, "arm64_mvn", XREG, XREG, NONE)

MINI_OP(OP_ARM64_SADD, "arm64_sadd", XREG, XREG, XREG)
MINI_OP(OP_ARM64_SADD2, "arm64_sadd2", XREG, XREG, XREG)
MINI_OP(OP_ARM64_UADD, "arm64_uadd", XREG, XREG, XREG)
Expand Down Expand Up @@ -1778,5 +1773,8 @@ MINI_OP(OP_WASM_ONESCOMPLEMENT, "wasm_onescomplement", XREG, XREG, NONE)
#endif

#if defined(TARGET_ARM64) || defined(TARGET_AMD64)
MINI_OP3(OP_BSL, "bitwise_select", XREG, XREG, XREG, XREG)
MINI_OP3(OP_BSL, "bitwise_select", XREG, XREG, XREG, XREG)
MINI_OP(OP_NEGATION, "negate", XREG, XREG, NONE)
MINI_OP(OP_NEGATION_SCALAR, "negate_scalar", XREG, XREG, NONE)
MINI_OP(OP_ONES_COMPLEMENT, "ones_complement", XREG, XREG, NONE)
#endif // TARGET_ARM64 || TARGET_AMD64
12 changes: 6 additions & 6 deletions src/mono/mono/mini/simd-intrinsics.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -383,16 +383,16 @@ emit_simd_ins_for_binary_op (MonoCompile *cfg, MonoClass *klass, MonoMethodSigna
static MonoInst*
emit_simd_ins_for_unary_op (MonoCompile *cfg, MonoClass *klass, MonoMethodSignature *fsig, MonoInst **args, MonoTypeEnum arg_type, int id)
{
#ifdef TARGET_ARM64
#if defined(TARGET_ARM64) || defined(TARGET_AMD64)
int op = -1;
switch (id){
case SN_Negate:
case SN_op_UnaryNegation:
op = OP_ARM64_XNEG;
op = OP_NEGATION;
break;
case SN_OnesComplement:
case SN_op_OnesComplement:
op = OP_ARM64_MVN;
op = OP_ONES_COMPLEMENT;
break;
default:
g_assert_not_reached ();
Expand Down Expand Up @@ -2628,11 +2628,11 @@ static SimdIntrinsic advsimd_methods [] = {
{SN_MultiplyWideningUpper, OP_ARM64_SMULL2, None, OP_ARM64_UMULL2},
{SN_MultiplyWideningUpperAndAdd, OP_ARM64_SMLAL2, None, OP_ARM64_UMLAL2},
{SN_MultiplyWideningUpperAndSubtract, OP_ARM64_SMLSL2, None, OP_ARM64_UMLSL2},
{SN_Negate, OP_ARM64_XNEG},
{SN_Negate, OP_NEGATION},
{SN_NegateSaturate, OP_XOP_OVR_X_X, INTRINS_AARCH64_ADV_SIMD_SQNEG},
{SN_NegateSaturateScalar, OP_XOP_OVR_SCALAR_X_X, INTRINS_AARCH64_ADV_SIMD_SQNEG},
{SN_NegateScalar, OP_ARM64_XNEG_SCALAR},
{SN_Not, OP_ARM64_MVN},
{SN_NegateScalar, OP_NEGATION_SCALAR},
{SN_Not, OP_ONES_COMPLEMENT},
{SN_Or, OP_XBINOP_FORCEINT, XBINOP_FORCEINT_OR},
{SN_OrNot, OP_XBINOP_FORCEINT, XBINOP_FORCEINT_ORNOT},
{SN_PolynomialMultiply, OP_XOP_OVR_X_X_X, INTRINS_AARCH64_ADV_SIMD_PMUL},
Expand Down

0 comments on commit 9bc025d

Please sign in to comment.