fix native linux/arm failure (#102760)

dotnet · May 29, 2024 · 9c9155d · 9c9155d
1 parent 480d48c
commit 9c9155d
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Showing 2 changed files with 13 additions and 6 deletions.
diff --git a/src/coreclr/jit/target.h b/src/coreclr/jit/target.h
@@ -371,24 +371,30 @@ static bool operator>(regMaskTP first, regMaskTP second)
     return first.getLow() > second.getLow();
 }
 
-static regMaskTP operator<<(regMaskTP& first, const int b)
+static regMaskTP operator<<(regMaskTP first, const int b)
 {
     regMaskTP result(first.getLow() << b);
     return result;
 }
 
-static regMaskTP operator>>(regMaskTP& first, const int b)
+static regMaskTP& operator<<=(regMaskTP& first, const int b)
+{
+    first = first << b;
+    return first;
+}
+#endif
+
+static regMaskTP operator>>(regMaskTP first, const int b)
 {
     regMaskTP result(first.getLow() >> b);
     return result;
 }
 
-static regMaskTP& operator<<=(regMaskTP& first, const int b)
+static regMaskTP& operator>>=(regMaskTP& first, const int b)
 {
-    first = first << b;
+    first = first >> b;
     return first;
 }
-#endif
 
 static regMaskTP operator~(regMaskTP first)
 {

diff --git a/src/coreclr/jit/unwind.cpp b/src/coreclr/jit/unwind.cpp
@@ -224,11 +224,12 @@ void Compiler::unwindPushPopMaskCFI(regMaskTP regMask, bool isFloat)
         // because LLVM only know about D0-D31.
         // As such pairs Sx,Sx+1 are referenced as D0-D15 registers in DWARF
         // For that we process registers in pairs.
+        regBit >>= isFloat ? 2 : 1;
         regNum = isFloat ? REG_PREV(REG_PREV(regNum)) : REG_PREV(regNum);
 #else
+        regBit >>= 1;
         regNum = REG_PREV(regNum);
 #endif
-        regBit = genRegMask(regNum);
     }
 }