ILC: Assertion failed '(unsigned)reg < ArrLen(regMasks)' in '...' during 'Generate code' (IL size 6; hash 0x04901a61; FullOpts) #102715
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area-CodeGen-coreclr
CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
Native AOT ARM32 Linux outerloop runs are on the floor due to hitting asserts in RyuJIT: https://dev.azure.com/dnceng-public/public/_build/results?buildId=687421&view=results
This regression was introduced in #102592 (the outerloop run at the commit right before the PR was clean).
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