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ARM64: Optimize pair of "ldr reg, [reg]" to ldp #35132

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kunalspathak opened this issue Apr 17, 2020 · 1 comment · Fixed by #84399
Closed

ARM64: Optimize pair of "ldr reg, [reg]" to ldp #35132

kunalspathak opened this issue Apr 17, 2020 · 1 comment · Fixed by #84399
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arch-arm64 area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
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Future

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@kunalspathak
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kunalspathak commented Apr 17, 2020 •
edited by BruceForstall
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ldr     x1, [x19,#16]
ldr     x2, [x19,#24]

can be combined into ldp if the loads are happening from subsequent memory.

ldp x1, x2, [x19, #16]

I collected no. of such ldr pairs in framework libraries and found approx. 5900 pairs in 3500 methods.

Details:

ldr_ldr_x_to_ldp.txt

category:cq
theme:optimization
skill-level:intermediate
cost:small
impact:medium
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@Dotnet-GitSync-Bot Dotnet-GitSync-Bot added the untriaged New issue has not been triaged by the area owner label Apr 17, 2020
@kunalspathak kunalspathak added arch-arm64 area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI labels Apr 17, 2020
@BruceForstall BruceForstall mentioned this issue Apr 18, 2020
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@kunalspathak kunalspathak modified the milestones: Future, 6.0.0 Nov 9, 2020
@kunalspathak kunalspathak removed the JitUntriaged CLR JIT issues needing additional triage label Nov 9, 2020
@JulieLeeMSFT JulieLeeMSFT modified the milestones: 6.0.0, Future Mar 23, 2021
@echesakov echesakov mentioned this issue Jul 8, 2021
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AndyJGraham added a commit to AndyJGraham/runtime that referenced this issue Oct 27, 2022
@AndyJGraham
Replace successive "ldr" and "str" instructions with "ldp" and "stp"
b88ff31 
This change serves to address the following four Github tickets:

    1. ARM64: Optimize pair of "ldr reg, [fp]" to ldp dotnet#35130
    2. ARM64: Optimize pair of "ldr reg, [reg]" to ldp dotnet#35132
    3. ARM64: Optimize pair of "str reg, [reg]" to stp dotnet#35133
    4. ARM64: Optimize pair of "str reg, [fp]" to stp  dotnet#35134

A technique was employed that involved detecting an optimisation
opportunity as instruction sequences were being generated.
The optimised instruction was then generated on top of the previous
instruction, with no second instruction generated. Thus, there were no
changes to instruction group size at “emission time” and no changes to
jump instructions.
@BruceForstall BruceForstall mentioned this issue Oct 27, 2022
Merged
BruceForstall pushed a commit to BruceForstall/runtime that referenced this issue Jan 12, 2023
@AndyJGraham @BruceForstall
Replace successive "ldr" and "str" instructions with "ldp" and "stp"
261c710 
This change serves to address the following four Github tickets:

    1. ARM64: Optimize pair of "ldr reg, [fp]" to ldp dotnet#35130
    2. ARM64: Optimize pair of "ldr reg, [reg]" to ldp dotnet#35132
    3. ARM64: Optimize pair of "str reg, [reg]" to stp dotnet#35133
    4. ARM64: Optimize pair of "str reg, [fp]" to stp  dotnet#35134

A technique was employed that involved detecting an optimisation
opportunity as instruction sequences were being generated.
The optimised instruction was then generated on top of the previous
instruction, with no second instruction generated. Thus, there were no
changes to instruction group size at “emission time” and no changes to
jump instructions.
kunalspathak pushed a commit that referenced this issue Jan 27, 2023
@AndyJGraham @BruceForstall @a74nh
Replace successive "ldr" and "str" instructions with "ldp" and "stp" (#…
acc409e 
…77540)

* Replace successive "ldr" and "str" instructions with "ldp" and "stp"

This change serves to address the following four Github tickets:

    1. ARM64: Optimize pair of "ldr reg, [fp]" to ldp #35130
    2. ARM64: Optimize pair of "ldr reg, [reg]" to ldp #35132
    3. ARM64: Optimize pair of "str reg, [reg]" to stp #35133
    4. ARM64: Optimize pair of "str reg, [fp]" to stp  #35134

A technique was employed that involved detecting an optimisation
opportunity as instruction sequences were being generated.
The optimised instruction was then generated on top of the previous
instruction, with no second instruction generated. Thus, there were no
changes to instruction group size at “emission time” and no changes to
jump instructions.

* No longer use a temporary buffer to build the optimized instruction.

* Addressed assorted review comments.

* Now optimizes ascending locations and decending locations with
consecutive STR and LDR instructions.

* Modification to remove last instructions.

* Ongoing improvements to remove previously-emitted instruction
during ldr / str optimization.

* Stopped optimization of consecutive instructions that straddled an instruction group boundary.

* Addressed code change requests in GitHub.

* Various fixes to ldp/stp optimization

Add code to update IP mappings when an instruction is removed.

* Delete unnecessary and incorrect assert

* Diagnostic change only, to confirm whether a theory is correct or
not when chasing an error.

* Revert "Diagnostic change only, to confirm whether a theory is correct or"

This reverts commit 4b0e51e.

* Do not merge. Temporarily removed calls to
"codeGen->genIPmappingUpdateForRemovedInstruction()".

Also, corrected minor bug in instruction numbering
when removing instructions during optimization.

* Modifications to better update the IP mapping table for a replaced instruction.

* Minor formatting change.

* Check for out of range offsets

* Don't optimise during prolog/epilog

* Fix windows build error

* IGF_HAS_REMOVED_INSTR is ARM64 only

* Add OptimizeLdrStr function

* Fix formatting

* Ensure local variables are tracked

* Don't peephole local variables

Co-authored-by: Bruce Forstall <brucefo@microsoft.com>
Co-authored-by: Alan Hayward <alan.hayward@arm.com>
Co-authored-by: Alan Hayward <a74nh@users.noreply.github.com>
@kunalspathak kunalspathak mentioned this issue Apr 6, 2023
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@ghost ghost added the in-pr There is an active PR which will close this issue when it is merged label Apr 6, 2023
@ghost ghost removed the in-pr There is an active PR which will close this issue when it is merged label Apr 8, 2023
@ghost ghost locked as resolved and limited conversation to collaborators May 9, 2023
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Perform ldr to ldp peephole optimization kunalspathak/runtime
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