-
Notifications
You must be signed in to change notification settings - Fork 5.3k
Closed
Labels
arch-arm32area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMICLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIenhancementProduct code improvement that does NOT require public API changes/additionsProduct code improvement that does NOT require public API changes/additions
Milestone
Description
For ARM32, double register number is not shown correctly in JitDump, JitDisasm and etc.
-
An example from coreclr unit test.
$ COMPlus_JitDisasm=DblAdd COMPlus_JitDump=DblAdd ./corerun tests/JIT/CodeGenBringUpTests/DblAdd/DblAdd.exe ...(omitted)... IN0001: 000006 EE30 0B01 vadd d0, d0, d2 ...(omitted)... IN0001: 000006 vadd d0, d0, d2However above instruction encoding
EE30 0B01meansvadd d0, d0, d1. -
Another example from recent PR for ryujit/arm32.
I was confused with below example ([RyuJIT/ARM32] Enable casting from small int to float coreclr#11643 (comment)) in the PR.IN0074: 000180 EEB8 4BC4 vcvt.i2d d8, s8This encoding
EEB8 4BC4meansvcvt.i2d d4, s8, i.e. single-float register number is correct, but double register number is incorrectly displayed.
Both LegacyJIT and RyuJIT have same problem.
category:implementation
theme:debug-dumps
skill-level:intermediate
cost:medium
Metadata
Metadata
Assignees
Labels
arch-arm32area-CodeGen-coreclrCLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMICLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMIenhancementProduct code improvement that does NOT require public API changes/additionsProduct code improvement that does NOT require public API changes/additions