[RISC-V] Fix invalid operand register in the emitted addition/subtraction code #102074
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…n and subtraction logic
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
If s1 would be a0 in this snippet, both ra and a1 would have the same value after right shifts, so the xor below would always return 0, no? |
Yes, this second shift was supposed to calculate whether the original second operand was negative but since the logic responsible for preserving the original's operands value wasn't prepared for the case where both of the operand registers were same and thus allowing the bug to happen. After fixing it it also implied that |
It fixes |
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@jakobbotsch Could you review this PR? Thank you. |
RISC-V testing failed on init-buildGIT: e464442 |
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/azp run runtime, runtime-coreclr superpmi-diffs |
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Azure Pipelines successfully started running 2 pipeline(s). |
…tion code (dotnet#102074) * [RISC-V] Added sext_w pseudoinstruction * [RISC-V] Inserted INS_sext_w pseudoinstruction * [RISC-V] Started implementing new overflow logic * [RISC-V] Finished preliminar implementation of bound checks * [RISC-V] Fixed invalid 32-bit instruction * [RISC-V] Fixed 32-bit addition overflow check assert * [RISC-V] More fixes in emitter * [RISC-V] Additional fixes * [RISC-V] Fixed triple same register problem in emitInsTernary addition and subtraction logic * [RISC-V] Added sext.w to disassembler * [RISC-V] Added comments * [RISC-V] Formatted code * [RISC-V] Fixed bug * [RISC-V] Fixed other bug * [RISC-V] Fixed bug causing the int32's version to never be emitted * [RISC-V] Fixed assert * [RISC-V] Improved comment * [RISC-V] Fixed comment * [RISC-V] Fixed temp reg acquiring * [RISC-V] Removed asserts * Fixed NodeInternalRegister's GetSingle method's comment * [RISC-V] Revoked more changes * [RISC-V] Revoked more changes * [RISC-V] Embedded sext_w into codegen * [RISC-V] Fixed some comments * [RISC-V] Added additional comment * [RISC-V] Improvements * [RISC-V] Added old comment
Fixes invalid operand register in the emitted addition/subtraction code when both of the operand registers are same. Slightly improves quality of the generated code. Also introduces
sext.wpreudoinstruction to replace double-shift sign extension snippetsExamples of old and new code:
Part of #84834, cc @dotnet/samsung