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Move more of the xplat hwintrinsic API implementation into managed code #103150

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Move more of the xplat hwintrinsic API implementation into managed code #103150

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4bab1d8
Minor cleanup of the Vector64/128/256/512 implementations to improve …
tannergooding Jun 5, 2024
0ed78a4
Ensure gtNewSimdSumNode maintains consistency with the software fallback
tannergooding Jun 6, 2024
69f352a
Ensure Vector128.Sum also does pairwise adds for floating-point
tannergooding Jun 6, 2024
4175905
Use the right type in the gtNewSimdBinOpNode call
tannergooding Jun 6, 2024
c465d2d
Don't regress fallback scenarios using AndNot
tannergooding Jun 6, 2024
a8f22e8
Move op_Addition and op_Subtraction for Vector64/128/256/512 into man…
tannergooding Jun 5, 2024
ad97c28
Move op_BitwiseAnd, op_BitwiseOr, op_ExclusiveOr, and op_OnesCompleme…
tannergooding Jun 5, 2024
5567cec
Move op_Division and op_Multiplication for Vector64/128/256/512 into …
tannergooding Jun 6, 2024
b784142
Move op_LeftShift, op_RightShift, and op_UnsignedRightShift for Vecto…
tannergooding Jun 6, 2024
4467b12
Move Abs and AndNot for Vector64/128/256/512 into managed
tannergooding Jun 6, 2024
99fdfdf
Move Vector<T> into managed
tannergooding Jun 7, 2024
64b5f9a
Use typeof where it was meant to be used
tannergooding Jun 7, 2024
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3 changes: 0 additions & 3 deletions src/coreclr/jit/fgbasic.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1403,7 +1403,6 @@ void Compiler::fgFindJumpTargets(const BYTE* codeAddr, IL_OFFSET codeSize, Fixed
case NI_Vector128_Create:
case NI_Vector128_CreateScalar:
case NI_Vector128_CreateScalarUnsafe:
case NI_VectorT_CreateBroadcast:
#if defined(TARGET_XARCH)
case NI_BMI1_TrailingZeroCount:
case NI_BMI1_X64_TrailingZeroCount:
Expand Down Expand Up @@ -1647,8 +1646,6 @@ void Compiler::fgFindJumpTargets(const BYTE* codeAddr, IL_OFFSET codeSize, Fixed
#endif // TARGET_ARM64
case NI_Vector128_get_AllBitsSet:
case NI_Vector128_get_One:
case NI_VectorT_get_AllBitsSet:
case NI_VectorT_get_One:
#if defined(TARGET_XARCH)
case NI_Vector256_get_AllBitsSet:
case NI_Vector256_get_One:
Expand Down
46 changes: 38 additions & 8 deletions src/coreclr/jit/gentree.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -25510,20 +25510,48 @@ GenTree* Compiler::gtNewSimdSumNode(var_types type, GenTree* op1, CorInfoType si
{
assert(IsBaselineVector512IsaSupportedDebugOnly());
GenTree* op1Dup = fgMakeMultiUse(&op1);
op1 = gtNewSimdGetUpperNode(TYP_SIMD32, op1, simdBaseJitType, simdSize);
op1Dup = gtNewSimdGetLowerNode(TYP_SIMD32, op1Dup, simdBaseJitType, simdSize);
simdSize = simdSize / 2;
op1 = gtNewSimdBinOpNode(GT_ADD, TYP_SIMD32, op1, op1Dup, simdBaseJitType, simdSize);

op1 = gtNewSimdGetLowerNode(TYP_SIMD32, op1, simdBaseJitType, simdSize);
op1Dup = gtNewSimdGetUpperNode(TYP_SIMD32, op1Dup, simdBaseJitType, simdSize);

if (varTypeIsFloating(simdBaseType))
{
// We need to ensure deterministic results which requires
// consistently adding values together. Since many operations
// end up operating on 128-bit lanes, we break sum the same way.

op1 = gtNewSimdSumNode(type, op1, simdBaseJitType, 32);
op1Dup = gtNewSimdSumNode(type, op1Dup, simdBaseJitType, 32);

return gtNewOperNode(GT_ADD, type, op1, op1Dup);
}

simdSize = 32;
op1 = gtNewSimdBinOpNode(GT_ADD, TYP_SIMD32, op1, op1Dup, simdBaseJitType, 32);
}

if (simdSize == 32)
{
assert(compIsaSupportedDebugOnly(InstructionSet_AVX2));
GenTree* op1Dup = fgMakeMultiUse(&op1);
op1 = gtNewSimdGetUpperNode(TYP_SIMD16, op1, simdBaseJitType, simdSize);
op1Dup = gtNewSimdGetLowerNode(TYP_SIMD16, op1Dup, simdBaseJitType, simdSize);
simdSize = simdSize / 2;
op1 = gtNewSimdBinOpNode(GT_ADD, TYP_SIMD16, op1, op1Dup, simdBaseJitType, simdSize);

op1 = gtNewSimdGetLowerNode(TYP_SIMD16, op1, simdBaseJitType, simdSize);
op1Dup = gtNewSimdGetUpperNode(TYP_SIMD16, op1Dup, simdBaseJitType, simdSize);

if (varTypeIsFloating(simdBaseType))
{
// We need to ensure deterministic results which requires
// consistently adding values together. Since many operations
// end up operating on 128-bit lanes, we break sum the same way.

op1 = gtNewSimdSumNode(type, op1, simdBaseJitType, 16);
op1Dup = gtNewSimdSumNode(type, op1Dup, simdBaseJitType, 16);

return gtNewOperNode(GT_ADD, type, op1, op1Dup);
}

simdSize = 16;
op1 = gtNewSimdBinOpNode(GT_ADD, TYP_SIMD16, op1, op1Dup, simdBaseJitType, 16);
}

assert(simdSize == 16);
Expand All @@ -25534,6 +25562,7 @@ GenTree* Compiler::gtNewSimdSumNode(var_types type, GenTree* op1, CorInfoType si
{
assert(compIsaSupportedDebugOnly(InstructionSet_SSE2));
GenTree* op1Shuffled = fgMakeMultiUse(&op1);

if (compOpportunisticallyDependsOn(InstructionSet_AVX))
{
assert(compIsaSupportedDebugOnly(InstructionSet_AVX));
Expand Down Expand Up @@ -25571,6 +25600,7 @@ GenTree* Compiler::gtNewSimdSumNode(var_types type, GenTree* op1, CorInfoType si
{
assert(compIsaSupportedDebugOnly(InstructionSet_SSE2));
GenTree* op1Shuffled = fgMakeMultiUse(&op1);

if (compOpportunisticallyDependsOn(InstructionSet_AVX))
{
assert(compIsaSupportedDebugOnly(InstructionSet_AVX));
Expand Down
179 changes: 0 additions & 179 deletions src/coreclr/jit/hwintrinsicarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -534,39 +534,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,

switch (intrinsic)
{
case NI_Vector64_Abs:
case NI_Vector128_Abs:
{
assert(sig->numArgs == 1);
op1 = impSIMDPopStack();
retNode = gtNewSimdAbsNode(retType, op1, simdBaseJitType, simdSize);
break;
}

case NI_Vector64_op_Addition:
case NI_Vector128_op_Addition:
{
assert(sig->numArgs == 2);

op2 = impSIMDPopStack();
op1 = impSIMDPopStack();

retNode = gtNewSimdBinOpNode(GT_ADD, retType, op1, op2, simdBaseJitType, simdSize);
break;
}

case NI_Vector64_AndNot:
case NI_Vector128_AndNot:
{
assert(sig->numArgs == 2);

op2 = impSIMDPopStack();
op1 = impSIMDPopStack();

retNode = gtNewSimdBinOpNode(GT_AND_NOT, retType, op1, op2, simdBaseJitType, simdSize);
break;
}

case NI_Vector128_AsVector:
{
assert(!sig->hasThis());
Expand Down Expand Up @@ -682,30 +649,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
break;
}

case NI_Vector64_op_BitwiseAnd:
case NI_Vector128_op_BitwiseAnd:
{
assert(sig->numArgs == 2);

op2 = impSIMDPopStack();
op1 = impSIMDPopStack();

retNode = gtNewSimdBinOpNode(GT_AND, retType, op1, op2, simdBaseJitType, simdSize);
break;
}

case NI_Vector64_op_BitwiseOr:
case NI_Vector128_op_BitwiseOr:
{
assert(sig->numArgs == 2);

op2 = impSIMDPopStack();
op1 = impSIMDPopStack();

retNode = gtNewSimdBinOpNode(GT_OR, retType, op1, op2, simdBaseJitType, simdSize);
break;
}

case NI_Vector64_Ceiling:
case NI_Vector128_Ceiling:
{
Expand Down Expand Up @@ -1062,32 +1005,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
break;
}

case NI_Vector64_op_Division:
case NI_Vector128_op_Division:
{
assert(sig->numArgs == 2);

if (!varTypeIsFloating(simdBaseType))
{
// We can't trivially handle division for integral types using SIMD
break;
}

CORINFO_ARG_LIST_HANDLE arg1 = sig->args;
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
var_types argType = TYP_UNKNOWN;
CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;

argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
op2 = getArgForHWIntrinsic(argType, argClass);

argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
op1 = getArgForHWIntrinsic(argType, argClass);

retNode = gtNewSimdBinOpNode(GT_DIV, retType, op1, op2, simdBaseJitType, simdSize);
break;
}

case NI_Vector64_Dot:
case NI_Vector128_Dot:
{
Expand Down Expand Up @@ -1653,32 +1570,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
break;
}

case NI_Vector64_op_Multiply:
case NI_Vector128_op_Multiply:
{
assert(sig->numArgs == 2);

if (varTypeIsLong(simdBaseType))
{
// TODO-ARM64-CQ: We should support long/ulong multiplication.
break;
}

CORINFO_ARG_LIST_HANDLE arg1 = sig->args;
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
var_types argType = TYP_UNKNOWN;
CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;

argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
op2 = getArgForHWIntrinsic(argType, argClass);

argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
op1 = getArgForHWIntrinsic(argType, argClass);

retNode = gtNewSimdBinOpNode(GT_MUL, retType, op1, op2, simdBaseJitType, simdSize);
break;
}

case NI_Vector64_MultiplyAddEstimate:
case NI_Vector128_MultiplyAddEstimate:
{
Expand Down Expand Up @@ -1725,15 +1616,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
break;
}

case NI_Vector64_op_OnesComplement:
case NI_Vector128_op_OnesComplement:
{
assert(sig->numArgs == 1);
op1 = impSIMDPopStack();
retNode = gtNewSimdUnOpNode(GT_NOT, retType, op1, simdBaseJitType, simdSize);
break;
}

case NI_Vector64_op_Inequality:
case NI_Vector128_op_Inequality:
{
Expand All @@ -1747,55 +1629,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
break;
}

case NI_Vector64_op_Subtraction:
case NI_Vector128_op_Subtraction:
{
assert(sig->numArgs == 2);

op2 = impSIMDPopStack();
op1 = impSIMDPopStack();

retNode = gtNewSimdBinOpNode(GT_SUB, retType, op1, op2, simdBaseJitType, simdSize);
break;
}

case NI_Vector64_op_LeftShift:
case NI_Vector128_op_LeftShift:
{
assert(sig->numArgs == 2);

op2 = impPopStack().val;
op1 = impSIMDPopStack();

retNode = gtNewSimdBinOpNode(GT_LSH, retType, op1, op2, simdBaseJitType, simdSize);
break;
}

case NI_Vector64_op_RightShift:
case NI_Vector128_op_RightShift:
{
assert(sig->numArgs == 2);
genTreeOps op = varTypeIsUnsigned(simdBaseType) ? GT_RSZ : GT_RSH;

op2 = impPopStack().val;
op1 = impSIMDPopStack();

retNode = gtNewSimdBinOpNode(op, retType, op1, op2, simdBaseJitType, simdSize);
break;
}

case NI_Vector64_op_UnsignedRightShift:
case NI_Vector128_op_UnsignedRightShift:
{
assert(sig->numArgs == 2);

op2 = impPopStack().val;
op1 = impSIMDPopStack();

retNode = gtNewSimdBinOpNode(GT_RSZ, retType, op1, op2, simdBaseJitType, simdSize);
break;
}

case NI_Vector64_Shuffle:
case NI_Vector128_Shuffle:
{
Expand Down Expand Up @@ -2205,18 +2038,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
break;
}

case NI_Vector64_op_ExclusiveOr:
case NI_Vector128_op_ExclusiveOr:
{
assert(sig->numArgs == 2);

op2 = impSIMDPopStack();
op1 = impSIMDPopStack();

retNode = gtNewSimdBinOpNode(GT_XOR, retType, op1, op2, simdBaseJitType, simdSize);
break;
}

case NI_AdvSimd_LoadVector64x2AndUnzip:
case NI_AdvSimd_LoadVector64x3AndUnzip:
case NI_AdvSimd_LoadVector64x4AndUnzip:
Expand Down
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