Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[LoongArch64] Synchronize with PR#103188 to fix the build error. #103390

Merged
merged 1 commit into from
Jun 17, 2024
Merged

[LoongArch64] Synchronize with PR#103188 to fix the build error. #103390

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 12 additions & 2 deletions src/coreclr/jit/lsraloongarch64.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -723,7 +723,12 @@ int LinearScan::BuildCall(GenTreeCall* call)
{
// Fast tail call - make sure that call target is always computed in volatile registers
// that will not be overridden by epilog sequence.
ctrlExprCandidates = (allRegs(TYP_INT) & (RBM_INT_CALLEE_TRASH & ~RBM_GSCOOKIE_TMP));
ctrlExprCandidates = allRegs(TYP_INT) & RBM_INT_CALLEE_TRASH.GetIntRegSet();
if (compiler->getNeedsGSSecurityCookie())
{
ctrlExprCandidates &=
~(genSingleTypeRegMask(REG_GSCOOKIE_TMP_0) | genSingleTypeRegMask(REG_GSCOOKIE_TMP_1));
}
assert(ctrlExprCandidates != RBM_NONE);
}
}
Expand All @@ -734,7 +739,12 @@ int LinearScan::BuildCall(GenTreeCall* call)
SingleTypeRegSet candidates = RBM_NONE;
if (call->IsFastTailCall())
{
candidates = (allRegs(TYP_INT) & (RBM_INT_CALLEE_TRASH & ~RBM_GSCOOKIE_TMP).GetIntRegSet());
candidates = allRegs(TYP_INT) & RBM_INT_CALLEE_TRASH.GetIntRegSet();
if (compiler->getNeedsGSSecurityCookie())
{
ctrlExprCandidates &=
~(genSingleTypeRegMask(REG_GSCOOKIE_TMP_0) | genSingleTypeRegMask(REG_GSCOOKIE_TMP_1));
}
assert(candidates != RBM_NONE);
}

Expand Down
1 change: 0 additions & 1 deletion src/coreclr/jit/targetloongarch64.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -110,7 +110,6 @@
// Temporary registers used for the GS cookie check.
#define REG_GSCOOKIE_TMP_0 REG_T0
#define REG_GSCOOKIE_TMP_1 REG_T1
#define RBM_GSCOOKIE_TMP (RBM_T0|RBM_T1)

// register to hold shift amount; no special register is required on LOONGARCH64.
#define REG_SHIFT REG_NA
Expand Down
Loading