-
Notifications
You must be signed in to change notification settings - Fork 4.8k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Use resumable leaf frames in CET hijack and in GC stress. #104198
Conversation
Tagging subscribers to this area: @mangod9 |
/azp run runtime-coreclr gcstress0x3-gcstress0xc |
Azure Pipelines successfully started running 1 pipeline(s). |
src/coreclr/vm/gccover.cpp
Outdated
DWORD_PTR retValRegs[1] = { 0 }; | ||
UINT numberOfRegs = 0; |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
DWORD_PTR retValRegs[1] = { 0 }; | |
UINT numberOfRegs = 0; | |
DWORD_PTR retValReg = 0; |
This can simplified since we are only protecting a single value.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I think with runtime async the need to protect two returns will be back fairly soon, so i did not simplify to strictly one return.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Thanks!
The stress failures on OSX arm64 look all preexisting. |
// The legacy X86 GC encoder does not encode the state of return registers at | ||
// call sites, so we must add an extra frame to protect returns. | ||
#ifdef TARGET_X86 | ||
DWORD_PTR retValReg = 0; | ||
|
||
if (afterCallProtect[0]) |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Given that we only need afterCallProtect
for x86 now, we can also delete the whole bunch of arch-specific code above to compute it for non-x86 platforms.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
There is a lot of cleanup possible since we’ve incremented r2r version.
I’d like to do that in a separate follow up change as that could be larger, but mostly mechanical and unlikely to break anything change.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
We would not need disassemble anything other than x86.
Perhaps x64 will merge with RISC and only x86 will be special.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
For non-x86 it will be just iterating over interruptible locations (partial or full interruptible - just different iterators) and stick HLT there.
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
Although that may still require disassembling - to ensure that hlt is on instruction edges.
Thanks!! |
Re: #102680 (comment)