[RISC-V] Turn off "V" in zlib-ng compilation #104776
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Our target ISA is rv64gc, not gcv. If kernel can't detect RISC-V extensions, zlib-ng defaults has_rvv to true, which crashes on hardware without vector instructions like VisionFive 2.
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carlossanlop
approved these changes
Jul 12, 2024
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Thank you for submitting the fix.
I can see WITH_RVV is among the advanced build options of zlib-ng and it is enabled by default. https://github.com/zlib-ng/zlib-ng?tab=readme-ov-file#advanced-build-options
Do we have any CI support that can confirm this change? Maybe runtime-community tests this platform?
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Do you know if |
clamp03
approved these changes
Jul 12, 2024
gbalykov
approved these changes
Jul 12, 2024
Our internal CI, here #104237 (comment) and on other RISC-V PRs lately. The "killed" tests fail on illegal instruction. |
Looks like it's RISC-V only. |
sirntar
approved these changes
Jul 12, 2024
AFAIK, the failures are not due to V extension. Could you share which illegal instruction is used in CI? |
viewizard
approved these changes
Jul 12, 2024
I'm on a different branch now but the illegal instruction came from |
RISC-V qemu-prio1-checked: 9344 / 9347 (99.97%)FailedKilledSkipped |
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CI hasn't reported bugs on qemu regarding the V extension before, so let's wait for the vf2 results. It will take some time (probably about 1.5 hours). |
RISC-V starfive-prio1-checked: 9347 / 9347 (100.00%)FailedKilledSkipped |
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Actually, I have the same failures on my vf2. In my case, I checked with gdb and found that the illegal instruction was |
Should this PR be closed without merging then? |
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@jkotas I think it is good to merge this PR now. We have a plan to optimize with V extension next year, so we will investigate V extension and enable V in zlib-ng compilation next year. Thank you. |
I am working on new tizen images for our CI, but they will be ready after my vacation plus a day or two to update our infrastructure. So the CI will run on the latest Tizen around 06/08. We are currently using the January version of Tizen, which is actually a bit outdated. |
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I have opened #104799 so that it is not forgotten |
Whether a |
You are right. |
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Our target ISA is rv64gc, not gcv. If kernel can't detect RISC-V extensions, zlib-ng defaults has_rvv to true, which crashes on hardware without vector instructions like VisionFive 2.
Part of #84834, cc @dotnet/samsung