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ARM64-SVE: Add AddRotateComplex, MultiplyAddRotateComplex #104926

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merged 11 commits into from
Jul 16, 2024
Merged

ARM64-SVE: Add AddRotateComplex, MultiplyAddRotateComplex #104926

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e1a5ac9
Add AddRotateComplex
amanasifkhalid Jul 15, 2024
d6a0afe
Add MultiplyAddRotateComplex; fix template
amanasifkhalid Jul 15, 2024
e503c4d
Merge from main
amanasifkhalid Jul 15, 2024
aecfb4f
Fix unit tests
amanasifkhalid Jul 15, 2024
f1841ca
Update trig tests
amanasifkhalid Jul 15, 2024
e5ccd78
style
amanasifkhalid Jul 15, 2024
9aa8755
Remote FMA intrin flag
amanasifkhalid Jul 15, 2024
c8bce7a
Tweak helpers
amanasifkhalid Jul 16, 2024
3443b5d
Fix LinearScan::BuildHWIntrinsic
amanasifkhalid Jul 16, 2024
cafe4a5
Fix helpers
amanasifkhalid Jul 16, 2024
de2ae6d
JIT feedback
amanasifkhalid Jul 16, 2024
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16 changes: 9 additions & 7 deletions src/coreclr/jit/codegenarm64test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6096,6 +6096,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
theEmitter->emitIns_R_PATTERN_I(INS_sve_uqincw, EA_SCALABLE, REG_V11, SVE_PATTERN_ALL, 16,
INS_OPTS_SCALABLE_S); // UQINCW <Zdn>.S{, <pattern>{, MUL #<imm>}}

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
// IF_SVE_BQ_2A
theEmitter->emitIns_R_R_I(INS_sve_ext, EA_SCALABLE, REG_V0, REG_V1, 0, INS_OPTS_SCALABLE_B,
INS_SCALABLE_OPTS_WITH_VECTOR_PAIR); // EXT <Zd>.B, {<Zn1>.B, <Zn2>.B }, #<imm>
Expand All @@ -6105,6 +6106,7 @@ void CodeGen::genArm64EmitterUnitTestsSve()
INS_SCALABLE_OPTS_WITH_VECTOR_PAIR); // EXT <Zd>.B, {<Zn1>.B, <Zn2>.B }, #<imm>
theEmitter->emitIns_R_R_I(INS_sve_ext, EA_SCALABLE, REG_V6, REG_FP_LAST, 255, INS_OPTS_SCALABLE_B,
INS_SCALABLE_OPTS_WITH_VECTOR_PAIR); // EXT <Zd>.B, {<Zn1>.B, <Zn2>.B }, #<imm>
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED

// IF_SVE_BQ_2B
theEmitter->emitIns_R_R_I(INS_sve_ext, EA_SCALABLE, REG_V0, REG_V1, 0,
Expand Down Expand Up @@ -8391,23 +8393,23 @@ void CodeGen::genArm64EmitterUnitTestsSve()
INS_OPTS_SCALABLE_D); // ST1B {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]

// IF_SVE_GP_3A
theEmitter->emitIns_R_R_R_I(INS_sve_fcadd, EA_SCALABLE, REG_V0, REG_P1, REG_V2, 90,
theEmitter->emitIns_R_R_R_I(INS_sve_fcadd, EA_SCALABLE, REG_V0, REG_P1, REG_V2, 0,
INS_OPTS_SCALABLE_H); // FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, <const>
theEmitter->emitIns_R_R_R_I(INS_sve_fcadd, EA_SCALABLE, REG_V0, REG_P1, REG_V2, 270,
theEmitter->emitIns_R_R_R_I(INS_sve_fcadd, EA_SCALABLE, REG_V0, REG_P1, REG_V2, 1,
INS_OPTS_SCALABLE_H); // FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, <const>
theEmitter->emitIns_R_R_R_I(INS_sve_fcadd, EA_SCALABLE, REG_V0, REG_P1, REG_V2, 270,
theEmitter->emitIns_R_R_R_I(INS_sve_fcadd, EA_SCALABLE, REG_V0, REG_P1, REG_V2, 1,
INS_OPTS_SCALABLE_S); // FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, <const>
theEmitter->emitIns_R_R_R_I(INS_sve_fcadd, EA_SCALABLE, REG_V0, REG_P1, REG_V2, 270,
theEmitter->emitIns_R_R_R_I(INS_sve_fcadd, EA_SCALABLE, REG_V0, REG_P1, REG_V2, 1,
INS_OPTS_SCALABLE_D); // FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, <const>

// IF_SVE_GT_4A
theEmitter->emitIns_R_R_R_R_I(INS_sve_fcmla, EA_SCALABLE, REG_V2, REG_P1, REG_V3, REG_V4, 0,
INS_OPTS_SCALABLE_H); // FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, <const>
theEmitter->emitIns_R_R_R_R_I(INS_sve_fcmla, EA_SCALABLE, REG_V0, REG_P2, REG_V1, REG_V5, 90,
theEmitter->emitIns_R_R_R_R_I(INS_sve_fcmla, EA_SCALABLE, REG_V0, REG_P2, REG_V1, REG_V5, 1,
INS_OPTS_SCALABLE_S); // FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, <const>
theEmitter->emitIns_R_R_R_R_I(INS_sve_fcmla, EA_SCALABLE, REG_V2, REG_P3, REG_V0, REG_V6, 180,
theEmitter->emitIns_R_R_R_R_I(INS_sve_fcmla, EA_SCALABLE, REG_V2, REG_P3, REG_V0, REG_V6, 2,
INS_OPTS_SCALABLE_D); // FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, <const>
theEmitter->emitIns_R_R_R_R_I(INS_sve_fcmla, EA_SCALABLE, REG_V2, REG_P3, REG_V0, REG_V6, 270,
theEmitter->emitIns_R_R_R_R_I(INS_sve_fcmla, EA_SCALABLE, REG_V2, REG_P3, REG_V0, REG_V6, 3,
INS_OPTS_SCALABLE_D); // FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, <const>

// IF_SVE_GI_4A
Expand Down
10 changes: 4 additions & 6 deletions src/coreclr/jit/emitarm64sve.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4410,7 +4410,6 @@ void emitter::emitInsSve_R_R_R(instruction ins,
/*****************************************************************************
*
* Add a SVE instruction referencing three registers and a constant.
* Do not call this directly. Use 'emitIns_R_R_R_I' instead.
*/

void emitter::emitInsSve_R_R_R_I(instruction ins,
Expand Down Expand Up @@ -5577,7 +5576,7 @@ void emitter::emitInsSve_R_R_R_I(instruction ins,
assert(isLowPredicateRegister(reg2));
assert(isVectorRegister(reg3));
assert(isScalableVectorSize(size));
imm = emitEncodeRotationImm90_or_270(imm);
assert(emitIsValidEncodedRotationImm90_or_270(imm));
fmt = IF_SVE_GP_3A;
break;

Expand Down Expand Up @@ -5860,7 +5859,6 @@ void emitter::emitInsSve_R_R_R_I_I(instruction ins,
/*****************************************************************************
*
* Add a SVE instruction referencing four registers.
* Do not call this directly. Use 'emitIns_R_R_R_R' instead.
*/

void emitter::emitInsSve_R_R_R_R(instruction ins,
Expand Down Expand Up @@ -6991,7 +6989,7 @@ void emitter::emitInsSve_R_R_R_R_I(instruction ins,
assert(isVectorRegister(reg3));
assert(isVectorRegister(reg4));
assert(isScalableVectorSize(size));
imm = emitEncodeRotationImm0_to_270(imm);
assert(emitIsValidEncodedRotationImm0_to_270(imm));
fmt = IF_SVE_GT_4A;
break;

Expand Down Expand Up @@ -9798,7 +9796,7 @@ void emitter::emitIns_PRFOP_R_R_I(instruction ins,

/*static*/ bool emitter::emitIsValidEncodedRotationImm90_or_270(ssize_t imm)
{
return (imm == 0) || (imm == 1);
return isValidUimm<1>(imm);
}

/************************************************************************
Expand Down Expand Up @@ -9867,7 +9865,7 @@ void emitter::emitIns_PRFOP_R_R_I(instruction ins,

/*static*/ bool emitter::emitIsValidEncodedRotationImm0_to_270(ssize_t imm)
{
return (imm >= 0) && (imm <= 3);
return isValidUimm<2>(imm);
}

/*****************************************************************************
Expand Down
10 changes: 10 additions & 0 deletions src/coreclr/jit/hwintrinsicarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -504,6 +504,16 @@ void HWIntrinsicInfo::lookupImmBounds(
immUpperBound = (int)SVE_PRFOP_CONST15;
break;

case NI_Sve_AddRotateComplex:
immLowerBound = 0;
immUpperBound = 1;
break;

case NI_Sve_MultiplyAddRotateComplex:
immLowerBound = 0;
immUpperBound = 3;
break;

case NI_Sve_TrigonometricMultiplyAddCoefficient:
immLowerBound = 0;
immUpperBound = 7;
Expand Down
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