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Move GenTreeVecCon and GenTreeMskCon under the respective FEATURE_* defines #104932

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merged 3 commits into from
Nov 8, 2024
Merged

Move GenTreeVecCon and GenTreeMskCon under the respective FEATURE_* defines #104932

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300dfc6
Move GenTreeVecCon and GenTreeMskCon under the respective FEATURE_* d…
tannergooding Jul 16, 2024
4560ef5
Apply formatting patch
tannergooding Jul 16, 2024
5804c18
Merge branch 'main' into cns_vecmsk
tannergooding Oct 30, 2024
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4 changes: 2 additions & 2 deletions src/coreclr/jit/assertionprop.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3007,7 +3007,7 @@ GenTree* Compiler::optVNBasedFoldConstExpr(BasicBlock* block, GenTree* parent, G
}
break;

#if FEATURE_SIMD
#if defined(FEATURE_SIMD)
case TYP_SIMD8:
{
simd8_t value = vnStore->ConstantValue<simd8_t>(vnCns);
Expand Down Expand Up @@ -3066,6 +3066,7 @@ GenTree* Compiler::optVNBasedFoldConstExpr(BasicBlock* block, GenTree* parent, G
break;

#endif // TARGET_XARCH
#endif // FEATURE_SIMD

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case TYP_MASK:
Expand All @@ -3080,7 +3081,6 @@ GenTree* Compiler::optVNBasedFoldConstExpr(BasicBlock* block, GenTree* parent, G
}
break;
#endif // FEATURE_MASKED_HW_INTRINSICS
#endif // FEATURE_SIMD

case TYP_BYREF:
// Do not support const byref optimization.
Expand Down
4 changes: 2 additions & 2 deletions src/coreclr/jit/codegenarm64.cpp
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Expand Up @@ -2405,6 +2405,7 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre
}
break;

#if defined(FEATURE_SIMD)
case GT_CNS_VEC:
{
GenTreeVecCon* vecCon = tree->AsVecCon();
Expand All @@ -2414,7 +2415,6 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre

switch (tree->TypeGet())
{
#if defined(FEATURE_SIMD)
case TYP_SIMD8:
case TYP_SIMD12:
case TYP_SIMD16:
Expand Down Expand Up @@ -2470,7 +2470,6 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre
}
break;
}
#endif // FEATURE_SIMD

default:
{
Expand All @@ -2480,6 +2479,7 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre

break;
}
#endif // FEATURE_SIMD

default:
unreached();
Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/jit/codegenarmarch.cpp
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Expand Up @@ -186,8 +186,12 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode)

case GT_CNS_INT:
case GT_CNS_DBL:
#if defined(FEATURE_SIMD)
case GT_CNS_VEC:
#endif // FEATURE_SIMD
#if defined(FEATURE_MASKED_HW_INTRINSICS)
case GT_CNS_MSK:
#endif // FEATURE_MASKED_HW_INTRINSICS
genSetRegToConst(targetReg, targetType, treeNode);
genProduceReg(treeNode);
break;
Expand Down
7 changes: 7 additions & 0 deletions src/coreclr/jit/codegencommon.cpp
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Expand Up @@ -8320,7 +8320,14 @@ void CodeGen::genCodeForReuseVal(GenTree* treeNode)
assert(treeNode->IsReuseRegVal());

// For now, this is only used for constant nodes.
#if defined(FEATURE_MASKED_HW_INTRINSICS)
assert(treeNode->OperIs(GT_CNS_INT, GT_CNS_DBL, GT_CNS_VEC, GT_CNS_MSK));
#elif defined(FEATURE_SIMD)
assert(treeNode->OperIs(GT_CNS_INT, GT_CNS_DBL, GT_CNS_VEC));
#else
assert(treeNode->OperIs(GT_CNS_INT, GT_CNS_DBL));
#endif

JITDUMP(" TreeNode is marked ReuseReg\n");

if (treeNode->IsIntegralConst(0) && GetEmitter()->emitCurIGnonEmpty())
Expand Down
16 changes: 8 additions & 8 deletions src/coreclr/jit/codegenxarch.cpp
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Expand Up @@ -724,27 +724,23 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, GenTre
}
break;

#if defined(FEATURE_SIMD)
case GT_CNS_VEC:
{
#if defined(FEATURE_SIMD)
GenTreeVecCon* vecCon = tree->AsVecCon();
genSetRegToConst(vecCon->GetRegNum(), targetType, &vecCon->gtSimdVal);
#else
unreached();
#endif
break;
}
#endif // FEATURE_SIMD

#if defined(FEATURE_MASKED_HW_INTRINSICS)
case GT_CNS_MSK:
{
#if defined(FEATURE_MASKED_HW_INTRINSICS)
GenTreeMskCon* mskCon = tree->AsMskCon();
genSetRegToConst(mskCon->GetRegNum(), targetType, &mskCon->gtSimdMaskVal);
#else
unreached();
#endif
break;
}
#endif // FEATURE_MASKED_HW_INTRINSICS

default:
unreached();
Expand Down Expand Up @@ -1906,8 +1902,12 @@ void CodeGen::genCodeForTreeNode(GenTree* treeNode)
FALLTHROUGH;

case GT_CNS_DBL:
#if defined(FEATURE_SIMD)
case GT_CNS_VEC:
#endif // FEATURE_SIMD
#if defined(FEATURE_MASKED_HW_INTRINSICS)
case GT_CNS_MSK:
#endif // FEATURE_MASKED_HW_INTRINSICS
genSetRegToConst(targetReg, targetType, treeNode);
genProduceReg(treeNode);
break;
Expand Down
9 changes: 8 additions & 1 deletion src/coreclr/jit/compiler.h
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Expand Up @@ -3057,11 +3057,14 @@ class Compiler

GenTree* gtNewSconNode(int CPX, CORINFO_MODULE_HANDLE scpHandle);

#if defined(FEATURE_SIMD)
GenTreeVecCon* gtNewVconNode(var_types type);

GenTreeVecCon* gtNewVconNode(var_types type, void* data);
#endif // FEATURE_SIMD

#if defined(FEATURE_MASKED_HW_INTRINSICS)
GenTreeMskCon* gtNewMskConNode(var_types type);
#endif // FEATURE_MASKED_HW_INTRINSICS

GenTree* gtNewAllBitsSetConNode(var_types type);

Expand Down Expand Up @@ -11800,8 +11803,12 @@ class GenTreeVisitor
case GT_CNS_LNG:
case GT_CNS_DBL:
case GT_CNS_STR:
#if defined(FEATURE_SIMD)
case GT_CNS_VEC:
#endif // FEATURE_SIMD
#if defined(FEATURE_MASKED_HW_INTRINSICS)
case GT_CNS_MSK:
#endif // FEATURE_MASKED_HW_INTRINSICS
case GT_MEMORYBARRIER:
case GT_JMP:
case GT_JCC:
Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/jit/compiler.hpp
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Expand Up @@ -4365,8 +4365,12 @@ void GenTree::VisitOperands(TVisitor visitor)
case GT_CNS_LNG:
case GT_CNS_DBL:
case GT_CNS_STR:
#if defined(FEATURE_SIMD)
case GT_CNS_VEC:
#endif // FEATURE_SIMD
#if defined(FEATURE_MASKED_HW_INTRINSICS)
case GT_CNS_MSK:
#endif // FEATURE_MASKED_HW_INTRINSICS
case GT_MEMORYBARRIER:
case GT_JMP:
case GT_JCC:
Expand Down
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