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JIT: Fix over-shifting logic when constant-folding AdvSimd.ShiftRight* and AdvSimd.ShiftLeft* #105847

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merged 8 commits into from
Aug 5, 2024
Merged

JIT: Fix over-shifting logic when constant-folding AdvSimd.ShiftRight* and AdvSimd.ShiftLeft* #105847

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7f6fc8f
Fix overshifting for RSZ folding
amanasifkhalid Aug 1, 2024
227197c
Add tests
amanasifkhalid Aug 1, 2024
1c58151
Fix for RSH folding too
amanasifkhalid Aug 1, 2024
1e257b8
Fix imms
amanasifkhalid Aug 1, 2024
a83832e
Add fallbacks for ShiftRight APIs; use them when imm is non-const/OOB
amanasifkhalid Aug 2, 2024
9c808d5
Test coverage
amanasifkhalid Aug 2, 2024
a2cbdd3
Add ShiftLeft fallback + tests
amanasifkhalid Aug 2, 2024
87b5533
Merge from main
amanasifkhalid Aug 2, 2024
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7 changes: 4 additions & 3 deletions src/coreclr/jit/hwintrinsic.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1667,11 +1667,12 @@ bool Compiler::CheckHWIntrinsicImmRange(NamedIntrinsic intrinsic,
switch (intrinsic)
{
case NI_AdvSimd_ShiftRightLogical:
case NI_AdvSimd_ShiftRightLogicalScalar:
case NI_AdvSimd_ShiftRightArithmetic:
case NI_AdvSimd_ShiftRightArithmeticScalar:
*useFallback = true;
break;

// TODO: Implement more AdvSimd fallbacks in Compiler::impNonConstFallback

default:
assert(*useFallback == false);
break;
Expand Down Expand Up @@ -1702,7 +1703,7 @@ bool Compiler::CheckHWIntrinsicImmRange(NamedIntrinsic intrinsic,
}
}
else
#endif // TARGET_XARCH
#endif // TARGET_X86
{
*useFallback = true;
return false;
Expand Down
30 changes: 28 additions & 2 deletions src/coreclr/jit/hwintrinsicarm64.cpp
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Expand Up @@ -567,17 +567,43 @@ GenTree* Compiler::impNonConstFallback(NamedIntrinsic intrinsic, var_types simdT
switch (intrinsic)
{
case NI_AdvSimd_ShiftRightLogical:
case NI_AdvSimd_ShiftRightLogicalScalar:
case NI_AdvSimd_ShiftRightArithmetic:
case NI_AdvSimd_ShiftRightArithmeticScalar:
{
// AdvSimd.ShiftRightLogical be replaced with AdvSimd.ShiftLogical, which takes op2 in a simd register
// AdvSimd.ShiftRight* be replaced with AdvSimd.Shift*, which takes op2 in a simd register

GenTree* op2 = impPopStack().val;
GenTree* op1 = impSIMDPopStack();

NamedIntrinsic fallbackIntrinsic;
switch (intrinsic)
{
case NI_AdvSimd_ShiftRightLogical:
fallbackIntrinsic = NI_AdvSimd_ShiftLogical;
break;

case NI_AdvSimd_ShiftRightLogicalScalar:
fallbackIntrinsic = NI_AdvSimd_ShiftLogicalScalar;
break;

case NI_AdvSimd_ShiftRightArithmetic:
fallbackIntrinsic = NI_AdvSimd_ShiftArithmetic;
break;

case NI_AdvSimd_ShiftRightArithmeticScalar:
fallbackIntrinsic = NI_AdvSimd_ShiftArithmeticScalar;
break;

default:
unreached();
}

// AdvSimd.ShiftLogical does right-shifts with negative immediates, hence the negation
GenTree* tmpOp =
gtNewSimdCreateBroadcastNode(simdType, gtNewOperNode(GT_NEG, genActualType(op2->TypeGet()), op2),
simdBaseJitType, genTypeSize(simdType));
return gtNewSimdHWIntrinsicNode(simdType, op1, tmpOp, NI_AdvSimd_ShiftLogical, simdBaseJitType,
return gtNewSimdHWIntrinsicNode(simdType, op1, tmpOp, fallbackIntrinsic, simdBaseJitType,
genTypeSize(simdType));
}

Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/hwintrinsiclistarm64.h
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Expand Up @@ -451,7 +451,7 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalSaturateScalar,
HARDWARE_INTRINSIC(AdvSimd, ShiftLogicalScalar, 8, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ushl, INS_ushl, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightAndInsert, -1, 3, true, {INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri, INS_sri}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightAndInsertScalar, 8, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sri, INS_sri, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmetic, -1, 2, true, {INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmetic, -1, 2, true, {INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_sshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_NoJmpTableIMM)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticAdd, -1, 3, true, {INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_ssra, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticAddScalar, 8, 3, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ssra, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticNarrowingSaturateLower, 8, 2, true, {INS_sqshrn, INS_invalid, INS_sqshrn, INS_invalid, INS_sqshrn, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand)
Expand All @@ -466,8 +466,8 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticRoundedNarrowingSaturateUn
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticRoundedNarrowingSaturateUnsignedUpper, 16, 3, true, {INS_invalid, INS_sqrshrun2, INS_invalid, INS_sqrshrun2, INS_invalid, INS_sqrshrun2, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticRoundedNarrowingSaturateUpper, 16, 3, true, {INS_sqrshrn2, INS_invalid, INS_sqrshrn2, INS_invalid, INS_sqrshrn2, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticRoundedScalar, 8, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_srshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticScalar, 8, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogical, -1, 2, true, {INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightArithmeticScalar, 8, 2, false, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sshr, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar|HW_Flag_NoJmpTableIMM)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogical, -1, 2, true, {INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_ushr, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_NoJmpTableIMM)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalAdd, -1, 3, true, {INS_usra, INS_usra, INS_usra, INS_usra, INS_usra, INS_usra, INS_usra, INS_usra, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalAddScalar, 8, 3, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_usra, INS_usra, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalNarrowingLower, 8, 2, true, {INS_shrn, INS_shrn, INS_shrn, INS_shrn, INS_shrn, INS_shrn, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand)
Expand All @@ -482,7 +482,7 @@ HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalRoundedNarrowingSaturateLower
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalRoundedNarrowingSaturateUpper, 16, 3, true, {INS_uqrshrn2, INS_uqrshrn2, INS_uqrshrn2, INS_uqrshrn2, INS_uqrshrn2, INS_uqrshrn2, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalRoundedNarrowingUpper, 16, 3, true, {INS_rshrn2, INS_rshrn2, INS_rshrn2, INS_rshrn2, INS_rshrn2, INS_rshrn2, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_HasRMWSemantics)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalRoundedScalar, 8, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_urshr, INS_urshr, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalScalar, 8, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ushr, INS_ushr, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar)
HARDWARE_INTRINSIC(AdvSimd, ShiftRightLogicalScalar, 8, 2, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_ushr, INS_ushr, INS_invalid, INS_invalid}, HW_Category_ShiftRightByImmediate, HW_Flag_HasImmediateOperand|HW_Flag_SIMDScalar|HW_Flag_NoJmpTableIMM)
HARDWARE_INTRINSIC(AdvSimd, SignExtendWideningLower, 8, 1, true, {INS_sxtl, INS_invalid, INS_sxtl, INS_invalid, INS_sxtl, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
HARDWARE_INTRINSIC(AdvSimd, SignExtendWideningUpper, 16, 1, true, {INS_sxtl2, INS_invalid, INS_sxtl2, INS_invalid, INS_sxtl2, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_BaseTypeFromFirstArg)
HARDWARE_INTRINSIC(AdvSimd, SqrtScalar, 8, 1, true, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_fsqrt, INS_fsqrt}, HW_Category_SIMD, HW_Flag_SIMDScalar)
Expand Down
8 changes: 4 additions & 4 deletions src/coreclr/jit/simd.h
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Expand Up @@ -668,10 +668,10 @@ void EvaluateUnarySimd(genTreeOps oper, bool scalar, var_types baseType, TSimd*
template <typename TBase>
TBase EvaluateBinaryScalarRSZ(TBase arg0, TBase arg1)
{
#if defined(TARGET_XARCH)
#if defined(TARGET_XARCH) || defined(TARGET_ARM64)
if ((arg1 < 0) || (arg1 >= (sizeof(TBase) * 8)))
{
// For SIMD, xarch allows overshifting and treats
// For SIMD, xarch and ARM64 allow overshifting and treat
// it as zeroing. So ensure we do the same here.
//
// The xplat APIs ensure the shiftAmount is masked
Expand Down Expand Up @@ -817,10 +817,10 @@ TBase EvaluateBinaryScalarSpecialized(genTreeOps oper, TBase arg0, TBase arg1)

case GT_RSH:
{
#if defined(TARGET_XARCH)
#if defined(TARGET_XARCH) || defined(TARGET_ARM64)
if ((arg1 < 0) || (arg1 >= (sizeof(TBase) * 8)))
{
// For SIMD, xarch allows overshifting and treats
// For SIMD, xarch and ARM64 allow overshifting and treat
// it as propagating the sign bit (returning Zero
// or AllBitsSet). So ensure we do the same here.
//
Expand Down
120 changes: 117 additions & 3 deletions src/tests/JIT/Regression/JitBlue/Runtime_105621/Runtime_105621.cs
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Expand Up @@ -14,19 +14,23 @@

public class Runtime_105621
{
private static byte getByteImmOOB() => 9;
private static byte getShortImmOOB() => 17;
private static byte getLongImmOOB() => 65;

[Fact]
public static void TestShiftByZero()
public static void TestShiftRightLogicalByZero()
{
if (AdvSimd.IsSupported)
{
var vr3 = Vector64.Create<byte>(0);
var vr3 = Vector64.Create<byte>(1);
var vr4 = AdvSimd.ShiftRightLogical(vr3, 0);
Assert.Equal(vr3, vr4);
}
}

[Fact]
public static void TestShiftToZero()
public static void TestShiftRightLogicalToZero()
{
if (AdvSimd.IsSupported)
{
Expand All @@ -35,4 +39,114 @@ public static void TestShiftToZero()
Assert.Equal(vr4, Vector64<byte>.Zero);
}
}

[Fact]
public static void TestShiftRightLogicalToZeroNonConst()
{
if (AdvSimd.IsSupported)
{
var vr3 = Vector64.Create<byte>(128);
var vr4 = AdvSimd.ShiftRightLogical(vr3, getByteImmOOB());
Assert.Equal(vr4, Vector64<byte>.Zero);
}
}

[Fact]
public static void TestShiftRightLogicalScalarByZero()
{
if (AdvSimd.IsSupported)
{
var vr3 = Vector64.Create<long>(1);
var vr4 = AdvSimd.ShiftRightLogicalScalar(vr3, 0);
Assert.Equal(vr3, vr4);
}
}

[Fact]
public static void TestShiftRightLogicalScalarToZero()
{
if (AdvSimd.IsSupported)
{
var vr3 = Vector64.Create<long>(128);
var vr4 = AdvSimd.ShiftRightLogicalScalar(vr3, 65);
Assert.Equal(vr4, Vector64<long>.Zero);
}
}

[Fact]
public static void TestShiftRightLogicalScalarToZeroNonConst()
{
if (AdvSimd.IsSupported)
{
var vr3 = Vector64.Create<long>(128);
var vr4 = AdvSimd.ShiftRightLogicalScalar(vr3, getLongImmOOB());
Assert.Equal(vr4, Vector64<long>.Zero);
}
}

[Fact]
public static void TestShiftRightArithmeticByZero()
{
if (AdvSimd.IsSupported)
{
var vr3 = Vector128.Create<short>(1);
var vr4 = AdvSimd.ShiftRightArithmetic(vr3, 0);
Assert.Equal(vr3, vr4);
}
}

[Fact]
public static void TestShiftRightArithmeticToZero()
{
if (AdvSimd.IsSupported)
{
var vr3 = Vector128.Create<short>(128);
var vr4 = AdvSimd.ShiftRightArithmetic(vr3, 17);
Assert.Equal(vr4, Vector128<short>.Zero);
}
}

[Fact]
public static void TestShiftRightArithmeticToZeroNonConst()
{
if (AdvSimd.IsSupported)
{
var vr3 = Vector128.Create<short>(128);
var vr4 = AdvSimd.ShiftRightArithmetic(vr3, getShortImmOOB());
Assert.Equal(vr4, Vector128<short>.Zero);
}
}

[Fact]
public static void TestShiftRightArithmeticScalarByZero()
{
if (AdvSimd.IsSupported)
{
var vr3 = Vector64.Create<long>(1);
var vr4 = AdvSimd.ShiftRightArithmeticScalar(vr3, 0);
Assert.Equal(vr3, vr4);
}
}

[Fact]
public static void TestShiftRightArithmeticScalarToZero()
{
if (AdvSimd.IsSupported)
{
var vr3 = Vector64.Create<long>(128);
var vr4 = AdvSimd.ShiftRightArithmeticScalar(vr3, 65);
Assert.Equal(vr4, Vector64<long>.Zero);
}
}

[Fact]
public static void TestShiftRightArithmeticScalarToZeroNonConst()
{
if (AdvSimd.IsSupported)
{
var vr3 = Vector64.Create<long>(128);
var vr4 = AdvSimd.ShiftRightArithmeticScalar(vr3, getLongImmOOB());
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Could you also add equivalent tests for ShiftLeftLogical and ShiftLeftLogicalScalar?

It should help ensure we don't have +1 more issues to handle from some missed edge case and will help ensure correct behavior in any future refactorings.

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Sure thing, looks like ShiftLeft* suffers from the same issues we ran into initially with ShiftRight*. In Debug, we don't use ShiftLogical as a fallback intrinsic, and we end up throwing an exception for out-of-range immediates. In Release, we constant-fold GT_LSH operands, but we don't allow over-shifting on ARM64, so the constant-folded behavior doesn't match what ShiftLogical would do. I'll add the fallback implementation in this PR to fix this in one go.

Assert.Equal(vr4, Vector64<long>.Zero);
}
}
}
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