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LoongArch is a NEW ISA which is different from MIPS #113564
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reference:https://docs.kernel.org/arch/loongarch/introduction.html Introduction to LoongArch
src/coreclr/jit/codegenlinear.cpp
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// For LoongArch64's ISA which is a RISC ISA which is different from any other existing ones, | ||
// even the instructions of 32bits operation need the upper 32bits be sign-extended to 64 bits. |
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The comment should be saying "LoongArch64 is using the same mechanism with MIPS64 in this scenario"
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@shushanhf Can you help to clarify the meaning of this comment?
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Can be change to:
LoongArch64 is using the similar mechanism with MIPS64 in this scenario
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Can be change to: LoongArch64 is using the similar mechanism with MIPS64 in this scenario
The problem is LoongArch64 does NOT have this mechanism (except for division instructions). So this would be still incorrect.
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Can be change to: LoongArch64 is using the similar mechanism with MIPS64 in this scenario
Yes, here LA64 has to keep similar mechanism with MIPS64.
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Can be change to: LoongArch64 is using the similar mechanism with MIPS64 in this scenario
The problem is LoongArch64 does NOT have this mechanism (except for division instructions). So this would be still incorrect.
Although the LA64 is not same with MIPS64 compeletely, liking you said there are still some instructions needing the upper 32bits be sign-extended to 64 bits, we have to keep the similar mechanism for LA64.
If you delete these code it will introduce some errors when you running the test cases.
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Marking "changes requested" as the modified comment is still incorrect.
cc @dotnet/samsung |
Co-authored-by: Adeel Mujahid <3840695+am11@users.noreply.github.com>
reference:https://docs.kernel.org/arch/loongarch/introduction.html
Introduction to LoongArch