JIT: Handle x86 gs cookie checks before tailcalls

[jakobbotsch]

The code path assumed we didn't have tailcalls on x86, but we do see them for CEE_JMP specifically. In that case the GS cookie check may need a register in AOT scenarios, so give it one.

Fix #121133

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Pull Request Overview

This PR fixes a bug in the x86 GS cookie check logic by adding support for tail calls. Previously, the code asserted that tail calls were not supported on x86, but this was incorrect as explicit tail calls and CEE_JMP instructions can occur on this platform.

Key Changes

• Removed the incorrect assert(!tailCall) on x86 that prevented tail calls from being handled
• Added a tail call path that returns RBM_ESI (a callee-saved register) to avoid conflicts with argument registers
• Updated comment to reflect the handling of both regular calls and tail calls

[jakobbotsch]

PTAL @dotnet/jit-contrib. More edge cases around register picking for the GS cookie check. This kind of codegen that is not under LSRA's purview is clearly very hard to get right. If we make changes in the area again we should try hard to represent it as normal IR.

[jakobbotsch]

/ba-g Helix timeout