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Jit: fix some sources of x64 chk/rel diffs #39888

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merged 1 commit into from
Jul 24, 2020
Merged

Jit: fix some sources of x64 chk/rel diffs #39888

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2 changes: 0 additions & 2 deletions src/coreclr/src/jit/codegenlinear.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -344,7 +344,6 @@ void CodeGen::genCodeForBBlist()
needLabel = true;
}

#if defined(DEBUG) || defined(LATE_DISASM)
// We also want to start a new Instruction group by calling emitAddLabel below,
// when we need accurate bbWeights for this block in the emitter. We force this
// whenever our previous block was a BBJ_COND and it has a different weight than us.
Expand All @@ -356,7 +355,6 @@ void CodeGen::genCodeForBBlist()
{
needLabel = true;
}
#endif // DEBUG || LATE_DISASM

if (needLabel)
{
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6 changes: 4 additions & 2 deletions src/coreclr/src/jit/emitxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -163,8 +163,10 @@ bool emitter::IsDstSrcSrcAVXInstruction(instruction ins)

bool emitter::AreUpper32BitsZero(regNumber reg)
{
// Don't look back across IG boundaries (possible control flow)
if (emitCurIGinsCnt == 0)
// If there are no instructions in this IG, we can look back at
// the previous IG's instructions if this IG is an extension.
//
if ((emitCurIGinsCnt == 0) && ((emitCurIG->igFlags & IGF_EXTEND) == 0))
{
return false;
}
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