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Add initial CoreCLR compilation support for Apple Silicon #40435
Add initial CoreCLR compilation support for Apple Silicon #40435
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Where did these constants come from?
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This should probably use the bit field extract macros....
The constants come from Arm reference manual.
D13.2.36 ESR_EL1, Exception Syndrome Register (EL1)
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Can you please make these named constants or defines to make it clear?
E.g. ESR_EC_SHIFT for the 26 and EC_SVC for 0x15 or something like that.