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Updating Vector<T> to support nint and nuint #50832

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merged 19 commits into from
Apr 20, 2021
Merged

Updating Vector<T> to support nint and nuint #50832

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5f076b9
Refactoring GenTreeJitIntrinsic to expose SimdSize and SimdBaseType v…
tannergooding Apr 6, 2021
c3e5a9b
Updating the JIT to pass through the CORINFO_TYPE for hardware intrin…
tannergooding Apr 7, 2021
2cc9369
Adding support for Vector<nint> and Vector<nuint> to managed code
tannergooding Apr 7, 2021
93b1bea
Updating the vector tests to cover nint and nuint
tannergooding Apr 7, 2021
a5d0c68
Recognize Vector<nint> and Vector<nuint> in the JIT
tannergooding Apr 7, 2021
236a6b5
Updating Vector64/128/256<T> NotSupportedTest metadata to include typ…
tannergooding Apr 7, 2021
ed5db1f
Updating the Vector64/128/256<T> tests to have NotSupported validatio…
tannergooding Apr 7, 2021
35764d7
Splitting ThrowHelper.ThrowForUnsupportedVectorBaseType into separate…
tannergooding Apr 7, 2021
57fc73d
Updating Utf16Utility.Validation to directly use Vector<nuint>
tannergooding Apr 7, 2021
3d4fe63
Don't use the auxiliary type to hold a SIMD type, since it can be tri…
tannergooding Apr 8, 2021
fa2d443
Split the mono handling for ThrowForUnsupportedVectorBaseType into Th…
tannergooding Apr 8, 2021
18c2c1a
Add basic handling for MONO_TYPE_I and MONO_TYPE_U to simd-intrinsics.c
tannergooding Apr 8, 2021
b311562
Ensure simd-intrinsics.c in Mono handles `MONO_TYPE_I` and `MONO_TYPE…
tannergooding Apr 8, 2021
c150826
Ensure we don't assert when encountering synthesized Vector128<nint> …
tannergooding Apr 9, 2021
1ea8770
Applying formatting patch
tannergooding Apr 14, 2021
3b6f168
Fix the handling for Crc32 and Crc32C on ARM64
tannergooding Apr 15, 2021
0f4764d
Updating Mono mini-amd64 to handle MONO_TYPE_I and MONO_TYPE_U for SI…
tannergooding Apr 15, 2021
a657763
Handle OP_XCOMPARE.CMP_GE_UN for MONO_TYPE_U
tannergooding Apr 15, 2021
7f0dd03
Handle MONO_TYPE_I and MONO_TYPE_U for Vector types in mini-llvm
tannergooding Apr 15, 2021
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4 changes: 2 additions & 2 deletions docs/design/features/hw-intrinsics.md
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Expand Up @@ -83,8 +83,8 @@ Note that the x86/x64 implementation is shared, while currently the Arm64 intrin

The hardware intrinsics nodes are generally imported as `GenTreeHWIntrinsic` nodes, with the `GT_HWINTRINSIC` operator. On these nodes:
* The `gtHWIntrinsicId` field contains the intrinsic ID, as declared in the hardware intrinsics table
* The `gtSIMDBaseType` field indicates the "base type" (generic type argument).
* The `gtSIMDSize` field indicates the full byte width of the vector (e.g. 16 bytes for `Vector128<T>`).
* The `GetSimdBaseType` method indicates the "base type" (generic type argument).
* The `GetSimdSize` method indicates the full byte width of the vector (e.g. 16 bytes for `Vector128<T>`).

### Lowering

Expand Down
4 changes: 2 additions & 2 deletions src/coreclr/jit/assertionprop.cpp
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Expand Up @@ -2733,8 +2733,8 @@ GenTree* Compiler::optConstantAssertionProp(AssertionDsc* curAssertion,
LclVarDsc* varDsc = lvaGetDesc(lclNum);
var_types simdType = tree->TypeGet();
assert(varDsc->TypeGet() == simdType);
var_types baseType = varDsc->lvBaseType;
newTree = gtGetSIMDZero(simdType, baseType, varDsc->GetStructHnd());
CorInfoType simdBaseJitType = varDsc->GetSimdBaseJitType();
newTree = gtGetSIMDZero(simdType, simdBaseJitType, varDsc->GetStructHnd());
if (newTree == nullptr)
{
return nullptr;
Expand Down
38 changes: 19 additions & 19 deletions src/coreclr/jit/codegenarm64.cpp
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Expand Up @@ -3847,11 +3847,11 @@ void CodeGen::genEmitHelperCall(unsigned helper, int argSize, emitAttr retSize,
void CodeGen::genSIMDIntrinsic(GenTreeSIMD* simdNode)
{
// NYI for unsupported base types
if (simdNode->gtSIMDBaseType != TYP_INT && simdNode->gtSIMDBaseType != TYP_LONG &&
simdNode->gtSIMDBaseType != TYP_FLOAT && simdNode->gtSIMDBaseType != TYP_DOUBLE &&
simdNode->gtSIMDBaseType != TYP_USHORT && simdNode->gtSIMDBaseType != TYP_UBYTE &&
simdNode->gtSIMDBaseType != TYP_SHORT && simdNode->gtSIMDBaseType != TYP_BYTE &&
simdNode->gtSIMDBaseType != TYP_UINT && simdNode->gtSIMDBaseType != TYP_ULONG)
if (simdNode->GetSimdBaseType() != TYP_INT && simdNode->GetSimdBaseType() != TYP_LONG &&
simdNode->GetSimdBaseType() != TYP_FLOAT && simdNode->GetSimdBaseType() != TYP_DOUBLE &&
simdNode->GetSimdBaseType() != TYP_USHORT && simdNode->GetSimdBaseType() != TYP_UBYTE &&
simdNode->GetSimdBaseType() != TYP_SHORT && simdNode->GetSimdBaseType() != TYP_BYTE &&
simdNode->GetSimdBaseType() != TYP_UINT && simdNode->GetSimdBaseType() != TYP_ULONG)
{
// We don't need a base type for the Upper Save & Restore intrinsics, and we may find
// these implemented over lclVars created by CSE without full handle information (and
Expand Down Expand Up @@ -4068,7 +4068,7 @@ void CodeGen::genSIMDIntrinsicInit(GenTreeSIMD* simdNode)
assert(simdNode->gtSIMDIntrinsicID == SIMDIntrinsicInit);

GenTree* op1 = simdNode->gtGetOp1();
var_types baseType = simdNode->gtSIMDBaseType;
var_types baseType = simdNode->GetSimdBaseType();
regNumber targetReg = simdNode->GetRegNum();
assert(targetReg != REG_NA);
var_types targetType = simdNode->TypeGet();
Expand All @@ -4085,7 +4085,7 @@ void CodeGen::genSIMDIntrinsicInit(GenTreeSIMD* simdNode)
assert(genIsValidFloatReg(targetReg));
assert(genIsValidIntReg(op1Reg) || genIsValidFloatReg(op1Reg));

emitAttr attr = (simdNode->gtSIMDSize > 8) ? EA_16BYTE : EA_8BYTE;
emitAttr attr = (simdNode->GetSimdSize() > 8) ? EA_16BYTE : EA_8BYTE;
insOpts opt = genGetSimdInsOpt(attr, baseType);

if (opt == INS_OPTS_1D)
Expand Down Expand Up @@ -4123,7 +4123,7 @@ void CodeGen::genSIMDIntrinsicInitN(GenTreeSIMD* simdNode)

var_types targetType = simdNode->TypeGet();

var_types baseType = simdNode->gtSIMDBaseType;
var_types baseType = simdNode->GetSimdBaseType();

regNumber vectorReg = targetReg;

Expand Down Expand Up @@ -4151,7 +4151,7 @@ void CodeGen::genSIMDIntrinsicInitN(GenTreeSIMD* simdNode)
initCount++;
}

assert((initCount * baseTypeSize) <= simdNode->gtSIMDSize);
assert((initCount * baseTypeSize) <= simdNode->GetSimdSize());

if (initCount * baseTypeSize < EA_16BYTE)
{
Expand Down Expand Up @@ -4200,7 +4200,7 @@ void CodeGen::genSIMDIntrinsicUnOp(GenTreeSIMD* simdNode)
simdNode->gtSIMDIntrinsicID == SIMDIntrinsicConvertToInt64);

GenTree* op1 = simdNode->gtGetOp1();
var_types baseType = simdNode->gtSIMDBaseType;
var_types baseType = simdNode->GetSimdBaseType();
regNumber targetReg = simdNode->GetRegNum();
assert(targetReg != REG_NA);
var_types targetType = simdNode->TypeGet();
Expand All @@ -4212,7 +4212,7 @@ void CodeGen::genSIMDIntrinsicUnOp(GenTreeSIMD* simdNode)
assert(genIsValidFloatReg(targetReg));

instruction ins = getOpForSIMDIntrinsic(simdNode->gtSIMDIntrinsicID, baseType);
emitAttr attr = (simdNode->gtSIMDSize > 8) ? EA_16BYTE : EA_8BYTE;
emitAttr attr = (simdNode->GetSimdSize() > 8) ? EA_16BYTE : EA_8BYTE;
insOpts opt = (ins == INS_mov) ? INS_OPTS_NONE : genGetSimdInsOpt(attr, baseType);

GetEmitter()->emitIns_R_R(ins, attr, targetReg, op1Reg, opt);
Expand All @@ -4235,7 +4235,7 @@ void CodeGen::genSIMDIntrinsicWiden(GenTreeSIMD* simdNode)
(simdNode->gtSIMDIntrinsicID == SIMDIntrinsicWidenHi));

GenTree* op1 = simdNode->gtGetOp1();
var_types baseType = simdNode->gtSIMDBaseType;
var_types baseType = simdNode->GetSimdBaseType();
regNumber targetReg = simdNode->GetRegNum();
assert(targetReg != REG_NA);
var_types simdType = simdNode->TypeGet();
Expand Down Expand Up @@ -4271,7 +4271,7 @@ void CodeGen::genSIMDIntrinsicNarrow(GenTreeSIMD* simdNode)

GenTree* op1 = simdNode->gtGetOp1();
GenTree* op2 = simdNode->gtGetOp2();
var_types baseType = simdNode->gtSIMDBaseType;
var_types baseType = simdNode->GetSimdBaseType();
regNumber targetReg = simdNode->GetRegNum();
assert(targetReg != REG_NA);
var_types simdType = simdNode->TypeGet();
Expand All @@ -4285,7 +4285,7 @@ void CodeGen::genSIMDIntrinsicNarrow(GenTreeSIMD* simdNode)
assert(genIsValidFloatReg(op2Reg));
assert(genIsValidFloatReg(targetReg));
assert(op2Reg != targetReg);
assert(simdNode->gtSIMDSize == 16);
assert(simdNode->GetSimdSize() == 16);

instruction ins = getOpForSIMDIntrinsic(simdNode->gtSIMDIntrinsicID, baseType);
assert((ins == INS_fcvtn) || (ins == INS_xtn));
Expand Down Expand Up @@ -4344,7 +4344,7 @@ void CodeGen::genSIMDIntrinsicBinOp(GenTreeSIMD* simdNode)

GenTree* op1 = simdNode->gtGetOp1();
GenTree* op2 = simdNode->gtGetOp2();
var_types baseType = simdNode->gtSIMDBaseType;
var_types baseType = simdNode->GetSimdBaseType();
regNumber targetReg = simdNode->GetRegNum();
assert(targetReg != REG_NA);
var_types targetType = simdNode->TypeGet();
Expand All @@ -4360,7 +4360,7 @@ void CodeGen::genSIMDIntrinsicBinOp(GenTreeSIMD* simdNode)
// TODO-ARM64-CQ Contain integer constants where posible

instruction ins = getOpForSIMDIntrinsic(simdNode->gtSIMDIntrinsicID, baseType);
emitAttr attr = (simdNode->gtSIMDSize > 8) ? EA_16BYTE : EA_8BYTE;
emitAttr attr = (simdNode->GetSimdSize() > 8) ? EA_16BYTE : EA_8BYTE;
insOpts opt = genGetSimdInsOpt(attr, baseType);

GetEmitter()->emitIns_R_R_R(ins, attr, targetReg, op1Reg, op2Reg, opt);
Expand Down Expand Up @@ -4392,7 +4392,7 @@ void CodeGen::genSIMDIntrinsicGetItem(GenTreeSIMD* simdNode)
simdType = TYP_SIMD16;
}

var_types baseType = simdNode->gtSIMDBaseType;
var_types baseType = simdNode->GetSimdBaseType();
regNumber targetReg = simdNode->GetRegNum();
assert(targetReg != REG_NA);
var_types targetType = simdNode->TypeGet();
Expand Down Expand Up @@ -4569,14 +4569,14 @@ void CodeGen::genSIMDIntrinsicSetItem(GenTreeSIMD* simdNode)
GenTree* op1 = simdNode->gtGetOp1();
GenTree* op2 = simdNode->gtGetOp2();

var_types baseType = simdNode->gtSIMDBaseType;
var_types baseType = simdNode->GetSimdBaseType();
regNumber targetReg = simdNode->GetRegNum();
assert(targetReg != REG_NA);
var_types targetType = simdNode->TypeGet();
assert(varTypeIsSIMD(targetType));

assert(op2->TypeGet() == baseType);
assert(simdNode->gtSIMDSize >= ((index + 1) * genTypeSize(baseType)));
assert(simdNode->GetSimdSize() >= ((index + 1) * genTypeSize(baseType)));

genConsumeOperands(simdNode);
regNumber op1Reg = op1->GetRegNum();
Expand Down
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