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Generate proper DWARF reg num for ARM32 #57443

Merged
merged 3 commits into from
Aug 16, 2021
Merged

Generate proper DWARF reg num for ARM32 #57443

merged 3 commits into from
Aug 16, 2021

Commits on Aug 15, 2021

  1. Generate proper DWARF reg num for ARM32 

    After introduction of VFP-v3 ARM S0-S31 no longer can be generated using LLVM because  numbering of registers to start from 256 and only D0-D31 are used.
So this change encode S0 as D0, S2 as D1, etc. Also use reg nums for DXX registers.
This change fix generation of CFI codes,
which trigger issue with generation of DWARF using LLVM in NativeAOT
See https://developer.arm.com/documentation/ihi0040/c/?lang=en#dwarf-register-names
See dotnet/runtimelab#1388
    @kant2002
    kant2002 committed Aug 15, 2021
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Commits on Aug 16, 2021

  1. Rearrange code as per suggestions from PR

    @kant2002
    kant2002 committed Aug 16, 2021
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  2. Fix formatting

    @kant2002
    kant2002 committed Aug 16, 2021
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