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Fix clr build on illumos-x64 #82183

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merged 4 commits into from
Feb 16, 2023
Merged

Fix clr build on illumos-x64 #82183

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b3d8eec
Fix clr build on illumos-x64
am11 Feb 15, 2023
e3fd88b
Keep in sync with codeman
am11 Feb 16, 2023
4bbc3f7
Use CPUID_XXX
am11 Feb 16, 2023
8be8f50
.
am11 Feb 16, 2023
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58 changes: 29 additions & 29 deletions src/coreclr/nativeaot/Runtime/startup.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -189,63 +189,63 @@ bool DetectCPUFeatures()

int cpuidInfo[4];

const int EAX = 0;
const int EBX = 1;
const int ECX = 2;
const int EDX = 3;
const int CPUID_EAX = 0;
const int CPUID_EBX = 1;
const int CPUID_ECX = 2;
const int CPUID_EDX = 3;

__cpuid(cpuidInfo, 0x00000000);
uint32_t maxCpuId = static_cast<uint32_t>(cpuidInfo[EAX]);
uint32_t maxCpuId = static_cast<uint32_t>(cpuidInfo[CPUID_EAX]);

if (maxCpuId >= 1)
{
__cpuid(cpuidInfo, 0x00000001);

if (((cpuidInfo[EDX] & (1 << 25)) != 0) && ((cpuidInfo[EDX] & (1 << 26)) != 0)) // SSE & SSE2
if (((cpuidInfo[CPUID_EDX] & (1 << 25)) != 0) && ((cpuidInfo[CPUID_EDX] & (1 << 26)) != 0)) // SSE & SSE2
{
if ((cpuidInfo[ECX] & (1 << 25)) != 0) // AESNI
if ((cpuidInfo[CPUID_ECX] & (1 << 25)) != 0) // AESNI
{
g_cpuFeatures |= XArchIntrinsicConstants_Aes;
}

if ((cpuidInfo[ECX] & (1 << 1)) != 0) // PCLMULQDQ
if ((cpuidInfo[CPUID_ECX] & (1 << 1)) != 0) // PCLMULQDQ
{
g_cpuFeatures |= XArchIntrinsicConstants_Pclmulqdq;
}

if ((cpuidInfo[ECX] & (1 << 0)) != 0) // SSE3
if ((cpuidInfo[CPUID_ECX] & (1 << 0)) != 0) // SSE3
{
g_cpuFeatures |= XArchIntrinsicConstants_Sse3;

if ((cpuidInfo[ECX] & (1 << 9)) != 0) // SSSE3
if ((cpuidInfo[CPUID_ECX] & (1 << 9)) != 0) // SSSE3
{
g_cpuFeatures |= XArchIntrinsicConstants_Ssse3;

if ((cpuidInfo[ECX] & (1 << 19)) != 0) // SSE4.1
if ((cpuidInfo[CPUID_ECX] & (1 << 19)) != 0) // SSE4.1
{
g_cpuFeatures |= XArchIntrinsicConstants_Sse41;

if ((cpuidInfo[ECX] & (1 << 20)) != 0) // SSE4.2
if ((cpuidInfo[CPUID_ECX] & (1 << 20)) != 0) // SSE4.2
{
g_cpuFeatures |= XArchIntrinsicConstants_Sse42;

if ((cpuidInfo[ECX] & (1 << 22)) != 0) // MOVBE
if ((cpuidInfo[CPUID_ECX] & (1 << 22)) != 0) // MOVBE
{
g_cpuFeatures |= XArchIntrinsicConstants_Movbe;
}

if ((cpuidInfo[ECX] & (1 << 23)) != 0) // POPCNT
if ((cpuidInfo[CPUID_ECX] & (1 << 23)) != 0) // POPCNT
{
g_cpuFeatures |= XArchIntrinsicConstants_Popcnt;
}

if (((cpuidInfo[ECX] & (1 << 27)) != 0) && ((cpuidInfo[ECX] & (1 << 28)) != 0)) // OSXSAVE & AVX
if (((cpuidInfo[CPUID_ECX] & (1 << 27)) != 0) && ((cpuidInfo[CPUID_ECX] & (1 << 28)) != 0)) // OSXSAVE & AVX
{
if (PalIsAvxEnabled() && (xmmYmmStateSupport() == 1))
{
g_cpuFeatures |= XArchIntrinsicConstants_Avx;

if ((cpuidInfo[ECX] & (1 << 12)) != 0) // FMA
if ((cpuidInfo[CPUID_ECX] & (1 << 12)) != 0) // FMA
{
g_cpuFeatures |= XArchIntrinsicConstants_Fma;
}
Expand All @@ -254,30 +254,30 @@ bool DetectCPUFeatures()
{
__cpuidex(cpuidInfo, 0x00000007, 0x00000000);

if ((cpuidInfo[EBX] & (1 << 5)) != 0) // AVX2
if ((cpuidInfo[CPUID_EBX] & (1 << 5)) != 0) // AVX2
{
g_cpuFeatures |= XArchIntrinsicConstants_Avx2;

__cpuidex(cpuidInfo, 0x00000007, 0x00000001);
if ((cpuidInfo[EAX] & (1 << 4)) != 0) // AVX-VNNI
if ((cpuidInfo[CPUID_EAX] & (1 << 4)) != 0) // AVX-VNNI
{
g_cpuFeatures |= XArchIntrinsicConstants_AvxVnni;
}

if (PalIsAvx512Enabled() && (avx512StateSupport() == 1)) // XGETBV XRC0[7:5] == 111
{
if ((cpuidInfo[EBX] & (1 << 16)) != 0) // AVX512F
if ((cpuidInfo[CPUID_EBX] & (1 << 16)) != 0) // AVX512F
{
g_cpuFeatures |= XArchIntrinsicConstants_Avx512f;

bool isAVX512_VLSupported = false;
if ((cpuidInfo[EBX] & (1 << 31)) != 0) // AVX512VL
if ((cpuidInfo[CPUID_EBX] & (1 << 31)) != 0) // AVX512VL
{
g_cpuFeatures |= XArchIntrinsicConstants_Avx512f_vl;
isAVX512_VLSupported = true;
}

if ((cpuidInfo[EBX] & (1 << 30)) != 0) // AVX512BW
if ((cpuidInfo[CPUID_EBX] & (1 << 30)) != 0) // AVX512BW
{
g_cpuFeatures |= XArchIntrinsicConstants_Avx512bw;
if (isAVX512_VLSupported)
Expand All @@ -286,7 +286,7 @@ bool DetectCPUFeatures()
}
}

if ((cpuidInfo[EBX] & (1 << 28)) != 0) // AVX512CD
if ((cpuidInfo[CPUID_EBX] & (1 << 28)) != 0) // AVX512CD
{
g_cpuFeatures |= XArchIntrinsicConstants_Avx512cd;
if (isAVX512_VLSupported)
Expand All @@ -295,7 +295,7 @@ bool DetectCPUFeatures()
}
}

if ((cpuidInfo[EBX] & (1 << 17)) != 0) // AVX512DQ
if ((cpuidInfo[CPUID_EBX] & (1 << 17)) != 0) // AVX512DQ
{
g_cpuFeatures |= XArchIntrinsicConstants_Avx512dq;
if (isAVX512_VLSupported)
Expand All @@ -319,35 +319,35 @@ bool DetectCPUFeatures()
{
__cpuidex(cpuidInfo, 0x00000007, 0x00000000);

if ((cpuidInfo[EBX] & (1 << 3)) != 0) // BMI1
if ((cpuidInfo[CPUID_EBX] & (1 << 3)) != 0) // BMI1
{
g_cpuFeatures |= XArchIntrinsicConstants_Bmi1;
}

if ((cpuidInfo[EBX] & (1 << 8)) != 0) // BMI2
if ((cpuidInfo[CPUID_EBX] & (1 << 8)) != 0) // BMI2
{
g_cpuFeatures |= XArchIntrinsicConstants_Bmi2;
}
}
}

__cpuid(cpuidInfo, 0x80000000);
uint32_t maxCpuIdEx = static_cast<uint32_t>(cpuidInfo[EAX]);
uint32_t maxCpuIdEx = static_cast<uint32_t>(cpuidInfo[CPUID_EAX]);

if (maxCpuIdEx >= 0x80000001)
{
__cpuid(cpuidInfo, 0x80000001);

if ((cpuidInfo[ECX] & (1 << 5)) != 0) // LZCNT
if ((cpuidInfo[CPUID_ECX] & (1 << 5)) != 0) // LZCNT
{
g_cpuFeatures |= XArchIntrinsicConstants_Lzcnt;
}

#ifdef HOST_AMD64
// AMD has a "fast" mode for fxsave/fxrstor, which omits the saving of xmm registers. The OS will enable this mode
// if it is supported. So if we continue to use fxsave/fxrstor, we must manually save/restore the xmm registers.
// fxsr_opt is bit 25 of EDX
if ((cpuidInfo[EDX] & (1 << 25)) != 0)
// fxsr_opt is bit 25 of CPUID_EDX
if ((cpuidInfo[CPUID_EDX] & (1 << 25)) != 0)
g_fHasFastFxsave = true;
#endif
}
Expand Down
6 changes: 1 addition & 5 deletions src/coreclr/vm/cgensys.h
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Original file line number Diff line number Diff line change
Expand Up @@ -104,16 +104,12 @@ extern "C" DWORD __stdcall xmmYmmStateSupport();
extern "C" DWORD __stdcall avx512StateSupport();
#endif

const int CPUID_EAX = 0;
const int CPUID_EBX = 1;
const int CPUID_ECX = 2;
const int CPUID_EDX = 3;

inline bool TargetHasAVXSupport()
{
#if (defined(TARGET_X86) || defined(TARGET_AMD64))
int cpuInfo[4];
__cpuid(cpuInfo, 0x00000001); // All x86/AMD64 targets support cpuid.
const int CPUID_ECX = 2;
return ((cpuInfo[CPUID_ECX] & (1 << 28)) != 0); // The AVX feature is ECX bit 28.
#endif // (defined(TARGET_X86) || defined(TARGET_AMD64))
return false;
Expand Down
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