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Optimization on LinearScan::buildPhysRegRecords #83862

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merged 3 commits into from
Apr 1, 2023
+21 −3
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Optimization on LinearScan::buildPhysRegRecords #83862

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582b399
Optimization on LinearScan::buildPhysRegRecords by skipping non-AVX51…
Ruihan-Yin Feb 10, 2023
c0f0712
code changes based on the reviews.
Ruihan-Yin Mar 27, 2023
42ae0c0
put the upper register group declaration in global
Ruihan-Yin Mar 28, 2023
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put the upper register group declaration in global 
fix the offset value when allocating upper registers, it should
be the length of the lower register group.
@Ruihan-Yin
Ruihan-Yin committed Mar 28, 2023

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commit 42ae0c09c6b9969d222fff75a7cc52ee0c9829d9
8 changes: 5 additions & 3 deletions src/coreclr/jit/lsrabuild.cpp
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Original file line number Diff line number Diff line change
@@ -1876,6 +1876,10 @@ const unsigned lsraRegOrderSize = ArrLen(lsraRegOrder);
// TODO-XARCH-AVX512 we might want to move this to be configured with the rbm variables too
static const regNumber lsraRegOrderFlt[] = {REG_VAR_ORDER_FLT};
const unsigned lsraRegOrderFltSize = ArrLen(lsraRegOrderFlt);
#if defined(TARGET_AMD64)
static const regNumber lsraRegOrderFltUpper[] = {REG_VAR_ORDER_FLT_UPPER};
const unsigned lsraRegOrderUpperFltSize = ArrLen(lsraRegOrderFltUpper);
#endif // TARGET_AMD64

//------------------------------------------------------------------------
// buildPhysRegRecords: Make an interval for each physical register
@@ -1902,13 +1906,11 @@ void LinearScan::buildPhysRegRecords()
#if defined(TARGET_AMD64)
if (compiler->canUseEvexEncoding())
{
const regNumber lsraRegOrderFltUpper[] = {REG_VAR_ORDER_FLT_UPPER};
const unsigned lsraRegOrderUpperFltSize = ArrLen(lsraRegOrderFltUpper);
for (unsigned int i = 0; i < lsraRegOrderUpperFltSize; i++)
{
regNumber reg = lsraRegOrderFltUpper[i];
RegRecord* curr = &physRegs[reg];
curr->regOrder = (unsigned char)(i + lsraRegOrderUpperFltSize);
curr->regOrder = (unsigned char)(i + lsraRegOrderFltSize);
}
}
#endif // TARGET_AMD64