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Cleanup some xarch emit logic #85536

Merged
merged 25 commits into from
May 2, 2023
Merged

Cleanup some xarch emit logic #85536

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295a300
Ensure floating-point codegen uses the VEX aware path
tannergooding Apr 27, 2023
cd59adb
Fix `IF_RRW_RRW_CNS` to be `IF_RWR_RRD_CNS`
tannergooding Apr 26, 2023
30a0ff9
Fixup emitfmtsxarch.h to have a more consistent layout
tannergooding Apr 28, 2023
9f62010
Allow querying the scheduling info for an insFormat
tannergooding Apr 28, 2023
4b42794
Ensure the new insFormats are handled
tannergooding Apr 28, 2023
e7cfb3e
Ensure we consistently use `emitInsModeFormat`
tannergooding Apr 27, 2023
d39df96
Ensure instructions which write to a mask register are EVEX only
tannergooding Apr 28, 2023
820e7fc
Improve REX.W handling for EVEX only instructions
tannergooding Apr 28, 2023
5dbc5af
Ensure that instructions use the right update mode and tuple type
tannergooding Apr 28, 2023
28cdc15
Apply formatting patch
tannergooding Apr 28, 2023
d13305d
Ensure DstSrcSrc is still handled correctly
tannergooding Apr 28, 2023
03814a2
Ensure BLSI/BLSR are still handled in emitOutputAM
tannergooding Apr 28, 2023
379b4ab
Use static_assert_no_msg
tannergooding Apr 28, 2023
9befa4f
Fixing the disassembly for IF_RRW_SHF
tannergooding Apr 28, 2023
d4f6a95
Fixing the IF check for shld/shrd on x86
tannergooding Apr 28, 2023
992a3f2
Use the correct name: inst_RV_TT_IV
tannergooding Apr 28, 2023
312c3e0
Ensure the 4 operand insFormats include the necessary constant
tannergooding Apr 29, 2023
fa8677b
Resolve an insFormat check on x86
tannergooding Apr 30, 2023
8e5475f
Ensure other SIMD code paths are VEX aware
tannergooding Apr 30, 2023
a81c703
Improve throughput by using a less expensive emitSizeOfInsDsc
tannergooding Apr 30, 2023
749db73
Merge remote-tracking branch 'dotnet/main' into xarch-improv
tannergooding Apr 30, 2023
2142183
Apply formatting patch
tannergooding Apr 30, 2023
8884ec7
Ensure emitSizeOfInsDsc_CNS is used for RWR_RRD_*RD_CNS
tannergooding Apr 30, 2023
a318b17
Ensure genSimd12UpperClear uses `andps` for the pre-SSE4.1 path
tannergooding May 1, 2023
1c60535
Merge remote-tracking branch 'dotnet/main' into xarch-improv
tannergooding May 1, 2023
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7 changes: 7 additions & 0 deletions src/coreclr/jit/codegen.h
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Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,9 @@ class CodeGen final : public CodeGenInterface
CORINFO_FIELD_HANDLE absBitmaskFlt;
CORINFO_FIELD_HANDLE absBitmaskDbl;

// Bit mask used in zeroing the 3rd element of a SIMD12
CORINFO_FIELD_HANDLE zroSimd12Elm3;

// Bit mask used in U8 -> double conversion to adjust the result.
CORINFO_FIELD_HANDLE u8ToDblBitmask;

Expand Down Expand Up @@ -925,6 +928,8 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
void genSimdUpperSave(GenTreeIntrinsic* node);
void genSimdUpperRestore(GenTreeIntrinsic* node);

void genSimd12UpperClear(regNumber tgtReg);

// TYP_SIMD12 (i.e Vector3 of size 12 bytes) is not a hardware supported size and requires
// two reads/writes on 64-bit targets. These routines abstract reading/writing of Vector3
// values through an indirection. Note that Vector3 locals allocated on stack would have
Expand Down Expand Up @@ -1532,6 +1537,8 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
void inst_RV_RV_IV(instruction ins, emitAttr size, regNumber reg1, regNumber reg2, unsigned ival);
void inst_RV_TT_IV(instruction ins, emitAttr attr, regNumber reg1, GenTree* rmOp, int ival);
void inst_RV_RV_TT(instruction ins, emitAttr size, regNumber targetReg, regNumber op1Reg, GenTree* op2, bool isRMW);
void inst_RV_RV_TT_IV(
instruction ins, emitAttr size, regNumber targetReg, regNumber op1Reg, GenTree* op2, int8_t ival, bool isRMW);
#endif

void inst_set_SV_var(GenTree* tree);
Expand Down
4 changes: 2 additions & 2 deletions src/coreclr/jit/codegencommon.cpp
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Expand Up @@ -4474,7 +4474,7 @@ void CodeGen::genZeroInitFltRegs(const regMaskTP& initFltRegs, const regMaskTP&
}
#elif defined(TARGET_XARCH)
// XORPS is the fastest and smallest way to initialize a XMM register to zero.
inst_RV_RV(INS_xorps, reg, reg, TYP_DOUBLE);
GetEmitter()->emitIns_SIMD_R_R_R(INS_xorps, EA_16BYTE, reg, reg, reg);
dblInitReg = reg;
#elif defined(TARGET_ARM64)
// We will just zero out the entire vector register. This sets it to a double/float zero value
Expand Down Expand Up @@ -4514,7 +4514,7 @@ void CodeGen::genZeroInitFltRegs(const regMaskTP& initFltRegs, const regMaskTP&
}
#elif defined(TARGET_XARCH)
// XORPS is the fastest and smallest way to initialize a XMM register to zero.
inst_RV_RV(INS_xorps, reg, reg, TYP_DOUBLE);
GetEmitter()->emitIns_SIMD_R_R_R(INS_xorps, EA_16BYTE, reg, reg, reg);
fltInitReg = reg;
#elif defined(TARGET_ARM64)
// We will just zero out the entire vector register. This sets it to a double/float zero value
Expand Down
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