Ensure that IF_*WR_RRD formats support 4-byte SIMD instructions #85594
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue DetailsThis resolves #85586 and resolves #85469 The general issue is that we have some scenarios where the instruction opcode is baselined at 4-bytes. In this case, we put the opcode in the This fixes the formats that are new to supporting this scenario with EVEX to handle it correctly.
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| code = insCodeMR(ins); | ||
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| if (EncodedBySSE38orSSE3A(ins)) | ||
| { | ||
| // Special case 4-byte AVX instructions as the | ||
| // regcode position conflicts with the opcode byte | ||
| dst = emitOutputAM(dst, id, code); | ||
| } | ||
| else | ||
| { | ||
| code = AddSimdPrefixIfNeeded(id, code, size); | ||
| regcode = (insEncodeReg345(id, id->idReg1(), size, &code) << 8); | ||
| dst = emitOutputAM(dst, id, code | regcode); | ||
| } | ||
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| sz = emitSizeOfInsDsc(id); |
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There's actually a bit of code duplication that exists between these format specific handlers and the general emitOutput** methods.
I want to get that cleaned up and it should be easier once #85536 goes in.
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/azp run runtime-coreclr jitstress-isas-x86, runtime-coreclr outerloop, runtime-coreclr jitstress, runtime-coreclr libraries-jitstress, Fuzzlyn |
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Azure Pipelines successfully started running 5 pipeline(s). |
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Fuzzlyn failure is pre-existing (at least back to .NET 8 P3): #85611 |
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Expecting a few JitStress failures due to #85608
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This resolves #85586 and resolves #85469
The general issue is that we have some scenarios where the instruction opcode is baselined at 4-bytes. In this case, we put the opcode in the
codebyte thatmodr/mis normally stored and so we can't pre-fill that with the regcode.This fixes the formats that are new to supporting this scenario with EVEX to handle it correctly.