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[RISC-V] NaN-box float arguments #93665

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merged 4 commits into from
Oct 21, 2023
Merged

[RISC-V] NaN-box float arguments #93665

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0290b73
[RISC-V] NaN-box the arguments passed to CallDescrWorkerInternal beca…
tomeksowi Oct 18, 2023
de178af
[RISC-V] Use variant of fmv.?.x appropriate for the size of the float…
tomeksowi Oct 18, 2023
fe923b9
[RISC-V] NaN-box floats in CopyStructToRegisters
tomeksowi Oct 18, 2023
66cc0e5
[RISC-V] Fix InvokeUtil::CopyArg to properly (sign|zero)-extend small…
tomeksowi Oct 20, 2023
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4 changes: 2 additions & 2 deletions src/coreclr/jit/codegenriscv64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7773,8 +7773,8 @@ void CodeGen::genFnPrologCalleeRegArgs()
assert(genIsValidFloatReg(varDsc->GetArgInitReg()));
if (genIsValidIntReg(varDsc->GetArgReg()))
{
GetEmitter()->emitIns_Mov(INS_fmv_d_x, EA_PTRSIZE, varDsc->GetArgInitReg(), varDsc->GetArgReg(),
false);
emitAttr size = (varDsc->TypeGet() == TYP_FLOAT) ? EA_4BYTE : EA_PTRSIZE;
GetEmitter()->emitIns_Mov(size, varDsc->GetArgInitReg(), varDsc->GetArgReg(), false);
regArgMaskLive &= ~genRegMask(varDsc->GetArgReg());
}
else if (varDsc->GetArgInitReg() > REG_ARG_FP_LAST)
Expand Down
17 changes: 12 additions & 5 deletions src/coreclr/vm/argdestination.h
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Expand Up @@ -98,6 +98,13 @@ class ArgDestination
// of the T value inside of the Nullable<T>
void CopyStructToRegisters(void *src, int fieldBytes, int destOffset)
{
static const INT64 NanBox =
#ifdef TARGET_RISCV64
0xffffffff00000000L;
#else
0L;
#endif // TARGET_RISCV64

_ASSERTE(IsStructPassedInRegs());
_ASSERTE(fieldBytes <= 16);

Expand All @@ -107,8 +114,8 @@ class ArgDestination
{ // struct with two floats.
_ASSERTE(m_argLocDescForStructInRegs->m_cFloatReg == 2);
_ASSERTE(m_argLocDescForStructInRegs->m_cGenReg == 0);
*(INT64*)((char*)m_base + argOfs) = *(INT32*)src;
*(INT64*)((char*)m_base + argOfs + 8) = *((INT32*)src + 1);
*(INT64*)((char*)m_base + argOfs) = NanBox | *(INT32*)src;
*(INT64*)((char*)m_base + argOfs + 8) = NanBox | *((INT32*)src + 1);
}
else if ((m_argLocDescForStructInRegs->m_structFields & STRUCT_FLOAT_FIELD_FIRST) != 0)
{ // the first field is float or double.
Expand All @@ -118,7 +125,7 @@ class ArgDestination

if ((m_argLocDescForStructInRegs->m_structFields & STRUCT_FIRST_FIELD_SIZE_IS8) == 0)
{
*(INT64*)((char*)m_base + argOfs) = *(INT32*)src; // the first field is float
*(INT64*)((char*)m_base + argOfs) = NanBox | *(INT32*)src; // the first field is float
}
else
{
Expand Down Expand Up @@ -146,7 +153,7 @@ class ArgDestination
if ((m_argLocDescForStructInRegs->m_structFields & STRUCT_HAS_8BYTES_FIELDS_MASK) == 0)
{
// the second field is float.
*(INT64*)((char*)m_base + argOfs) = destOffset == 0 ? *((INT32*)src + 1) : *(INT32*)src;
*(INT64*)((char*)m_base + argOfs) = NanBox | (destOffset == 0 ? *((INT32*)src + 1) : *(INT32*)src);
}
else
{
Expand All @@ -163,7 +170,7 @@ class ArgDestination
}
else
{
_ASSERTE(!"---------UNReachable-------LoongArch64!!!");
_ASSERTE(!"---------UNReachable-------LoongArch64/RISC-V64!!!");
}
}
#endif // !DACCESS_COMPILE
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8 changes: 7 additions & 1 deletion src/coreclr/vm/invokeutil.cpp
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Expand Up @@ -156,9 +156,15 @@ void InvokeUtil::CopyArg(TypeHandle th, PVOID argRef, ArgDestination *argDest) {
break;
}

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case ELEMENT_TYPE_R4:
#ifdef TARGET_RISCV64
_ASSERTE(argRef != NULL);
// NaN-box the register value or single-float instructions will treat it as NaN
*(INT64 *)pArgDst = 0xffffffff00000000L | *(INT32 *)argRef;
break;
#endif // TARGET_RISCV64
case ELEMENT_TYPE_I4:
case ELEMENT_TYPE_U4:
case ELEMENT_TYPE_R4:
IN_TARGET_32BIT(case ELEMENT_TYPE_U:)
IN_TARGET_32BIT(case ELEMENT_TYPE_I:)
{
Expand Down
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