JIT: ARM64 SVE format encodings, `SVE_IH_3A` to `SVE_JO_3A` #95994

TIHan · 2023-12-14T01:14:32Z

Contributes to #94549

Adds the following SVE formats:

Capstone is in red, Jit is in green

--- a/Untitled-1.txt
+++ b/Untitled-2.txt
@@ -1,99 +1,99 @@
-ld1d  { z5.d }, p3/z, [x4]
-ld1d  { z0.q }, p2/z, [x3, #5, mul vl]
-ld1w  { z0.s }, p2/z, [x3, #3, mul vl]
-ld1w  { z0.d }, p2/z, [x3, #3, mul vl]
-ld1w  { z0.q }, p2/z, [x3, #3, mul vl]
-ld1sw { z0.d }, p5/z, [x3, #4, mul vl]
-ld1sb { z3.h }, p0/z, [x2, #6, mul vl]
-ld1sb { z3.s }, p0/z, [x2, #6, mul vl]
-ld1sb { z3.d }, p0/z, [x2, #6, mul vl]
-ld1b  { z5.b }, p1/z, [x3, #7, mul vl]
-ld1b  { z5.h }, p1/z, [x3, #7, mul vl]
-ld1b  { z5.s }, p1/z, [x3, #7, mul vl]
-ld1b  { z5.d }, p1/z, [x3, #7, mul vl]
-ld1sh { z7.s }, p3/z, [x5, #2, mul vl]
-ld1sh { z7.d }, p3/z, [x5, #2, mul vl]
-ld1h  { z2.h }, p1/z, [x6, #1, mul vl]
-ld1h  { z2.s }, p1/z, [x6, #1, mul vl]
-ld1h  { z2.d }, p1/z, [x6, #1, mul vl]
-ldnf1d        { z0.d }, p0/z, [x0]
-ldnf1sw       { z0.d }, p0/z, [x0]
-ldnf1d        { z0.d }, p1/z, [x2, #5, mul vl]
-ldnf1sw       { z0.d }, p1/z, [x2, #5, mul vl]
-ldnf1sh       { z0.s }, p1/z, [x5, #5, mul vl]
-ldnf1w        { z0.s }, p2/z, [x4, #5, mul vl]
-ldnf1sh       { z0.d }, p1/z, [x5, #5, mul vl]
-ldnf1w        { z0.d }, p2/z, [x4, #5, mul vl]
-ldnf1h        { z1.h }, p3/z, [x2, #5, mul vl]
-ldnf1sb       { z0.h }, p4/z, [x1, #5, mul vl]
-ldnf1h        { z1.s }, p3/z, [x2, #5, mul vl]
-ldnf1sb       { z0.s }, p4/z, [x1, #5, mul vl]
-ldnf1h        { z1.d }, p3/z, [x2, #5, mul vl]
-ldnf1sb       { z0.d }, p4/z, [x1, #5, mul vl]
-ldnf1b        { z2.b }, p5/z, [x3, #-4, mul vl]
-ldnf1b        { z2.h }, p5/z, [x3, #-2, mul vl]
-ldnf1b        { z2.s }, p5/z, [x3, #2, mul vl]
-ldnf1b        { z2.d }, p5/z, [x3, #1, mul vl]
-ldnt1b        { z0.b }, p1/z, [x2, #-5, mul vl]
-ldnt1d        { z3.d }, p4/z, [x5, #-1, mul vl]
-ldnt1h        { z6.h }, p7/z, [x8]
-ldnt1w        { z1.s }, p2/z, [x3, #-8, mul vl]
-ld1rob        { z0.b }, p1/z, [x2]
-ld1rod        { z4.d }, p5/z, [x6, #-0x20]
-ld1roh        { z8.h }, p3/z, [x1, #-0x100]
-ld1row        { z3.s }, p4/z, [x0, #0xE0]
-ld1rqb        { z6.b }, p7/z, [x8, #0x40]
-ld1rqd        { z9.d }, p0/z, [x1, #-0x80]
-ld1rqh        { z4.h }, p5/z, [x6, #0x70]
-ld1rqw        { z3.s }, p2/z, [x1, #-0x10]
-ld2q  { z0.q, z1.q }, p1/z, [x2, #-0x10, mul vl]
-ld2q  { z0.q, z1.q }, p1/z, [x2, #0xE, mul vl]
-ld3q  { z0.q - z2.q }, p4/z, [x5, #-0x18, mul vl]
-ld3q  { z0.q - z2.q }, p4/z, [x5, #0x15, mul vl]
-ld4q  { z0.q - z3.q }, p5/z, [x3, #-0x20, mul vl]
-ld4q  { z0.q - z3.q }, p5/z, [x3, #0x1C, mul vl]
-ld2q  { z12.q, z13.q }, p1/z, [x2, #-0x10, mul vl]
-ld2q  { z13.q, z14.q }, p1/z, [x2, #0xE, mul vl]
-ld3q  { z14.q - z16.q }, p4/z, [x5, #-0x18, mul vl]
-ld3q  { z15.q - z17.q }, p4/z, [x5, #0x15, mul vl]
-ld4q  { z16.q - z19.q }, p5/z, [x3, #-0x20, mul vl]
-ld4q  { z27.q - z30.q }, p5/z, [x3, #0x1C, mul vl]
-ld4q  { z28.q - z31.q }, p5/z, [x3, #0x1C, mul vl]
-ld4q  { z29.q, z30.q, z31.q, z0.q }, p5/z, [x3, #0x1C, mul vl]
-ld4q  { z30.q, z31.q, z0.q, z1.q }, p5/z, [x3, #0x1C, mul vl]
-ld4q  { z31.q, z0.q, z1.q, z2.q }, p5/z, [x3, #0x1C, mul vl]
-ld2q  { z31.q, z0.q }, p1/z, [x2, #-0x10, mul vl]
-ld2b  { z0.b, z1.b }, p1/z, [x2, #-0x10, mul vl]
-ld2d  { z4.d, z5.d }, p5/z, [x7, #0xE, mul vl]
-ld2h  { z6.h, z7.h }, p5/z, [x4, #8, mul vl]
-ld2w  { z0.s, z1.s }, p0/z, [x1, #2, mul vl]
-ld3b  { z0.b - z2.b }, p0/z, [x0, #0x15, mul vl]
-ld3d  { z0.d - z2.d }, p0/z, [x0, #-0x18, mul vl]
-ld3h  { z0.h - z2.h }, p0/z, [x0, #0x15, mul vl]
-ld3w  { z0.s - z2.s }, p0/z, [x0, #-0x18, mul vl]
-ld4b  { z31.b, z0.b, z1.b, z2.b }, p2/z, [x1, #-0x20, mul vl]
-ld4d  { z8.d - z11.d }, p0/z, [x0, #0x1C, mul vl]
-ld4h  { z5.h - z8.h }, p4/z, [x3, #-0x20, mul vl]
-ld4w  { z0.s - z3.s }, p1/z, [x2, #0x1C, mul vl]
-st2q  { z0.q, z1.q }, p3, [x0, #-0x10, mul vl]
-st3q  { z2.q - z4.q }, p3, [x4, #0x15, mul vl]
-st4q  { z7.q - z10.q }, p6, [x5, #0x1C, mul vl]
-stnt1b        { z1.b }, p2, [x3, #4, mul vl]
-stnt1d        { z8.d }, p7, [x6, #5, mul vl]
-stnt1h        { z9.h }, p1, [x0, #-5, mul vl]
-stnt1w        { z0.s }, p0, [x2, #-7, mul vl]
-st1d  { z1.d }, p2, [x3, #4, mul vl]
-st1w  { z3.q }, p4, [x5, #6, mul vl]
-st1d  { z2.q }, p1, [x0]
-st2b  { z0.b, z1.b }, p1, [x2, #-0x10, mul vl]
-st2d  { z5.d, z6.d }, p4, [x3, #-0x10, mul vl]
-st2h  { z6.h, z7.h }, p7, [x8, #-0x10, mul vl]
-st2w  { z8.s, z9.s }, p1, [x9, #-0x10, mul vl]
-st3b  { z7.b - z9.b }, p6, [x5, #-0x18, mul vl]
-st3d  { z2.d - z4.d }, p3, [x4, #-0x18, mul vl]
-st3h  { z1.h - z3.h }, p2, [x3, #-0x18, mul vl]
-st3w  { z1.s - z3.s }, p3, [x8, #-0x18, mul vl]
-st4b  { z0.b - z3.b }, p0, [x0, #-0x20, mul vl]
-st4d  { z2.d - z5.d }, p0, [x1, #-0x20, mul vl]
-st4h  { z3.h - z6.h }, p5, [x2, #-0x20, mul vl]
-st4w  { z0.s - z3.s }, p1, [x5, #0x1C, mul vl]
\ No newline at end of file
+ld1d    { z5.d }, p3/z, [x4]
+ld1d    { z0.q }, p2/z, [x3, #5, mul vl]
+ld1w    { z0.s }, p2/z, [x3, #3, mul vl]
+ld1w    { z0.d }, p2/z, [x3, #3, mul vl]
+ld1w    { z0.q }, p2/z, [x3, #3, mul vl]
+ld1sw   { z0.d }, p5/z, [x3, #4, mul vl]
+ld1sb   { z3.h }, p0/z, [x2, #6, mul vl]
+ld1sb   { z3.s }, p0/z, [x2, #6, mul vl]
+ld1sb   { z3.d }, p0/z, [x2, #6, mul vl]
+ld1b    { z5.b }, p1/z, [x3, #7, mul vl]
+ld1b    { z5.h }, p1/z, [x3, #7, mul vl]
+ld1b    { z5.s }, p1/z, [x3, #7, mul vl]
+ld1b    { z5.d }, p1/z, [x3, #7, mul vl]
+ld1sh   { z7.s }, p3/z, [x5, #2, mul vl]
+ld1sh   { z7.d }, p3/z, [x5, #2, mul vl]
+ld1h    { z2.h }, p1/z, [x6, #1, mul vl]
+ld1h    { z2.s }, p1/z, [x6, #1, mul vl]
+ld1h    { z2.d }, p1/z, [x6, #1, mul vl]
+ldnf1d  { z0.d }, p0/z, [x0]
+ldnf1sw { z0.d }, p0/z, [x0]
+ldnf1d  { z0.d }, p1/z, [x2, #5, mul vl]
+ldnf1sw { z0.d }, p1/z, [x2, #5, mul vl]
+ldnf1sh { z0.s }, p1/z, [x5, #5, mul vl]
+ldnf1w  { z0.s }, p2/z, [x4, #5, mul vl]
+ldnf1sh { z0.d }, p1/z, [x5, #5, mul vl]
+ldnf1w  { z0.d }, p2/z, [x4, #5, mul vl]
+ldnf1h  { z1.h }, p3/z, [x2, #5, mul vl]
+ldnf1sb { z0.h }, p4/z, [x1, #5, mul vl]
+ldnf1h  { z1.s }, p3/z, [x2, #5, mul vl]
+ldnf1sb { z0.s }, p4/z, [x1, #5, mul vl]
+ldnf1h  { z1.d }, p3/z, [x2, #5, mul vl]
+ldnf1sb { z0.d }, p4/z, [x1, #5, mul vl]
+ldnf1b  { z2.b }, p5/z, [x3, #-4, mul vl]
+ldnf1b  { z2.h }, p5/z, [x3, #-2, mul vl]
+ldnf1b  { z2.s }, p5/z, [x3, #2, mul vl]
+ldnf1b  { z2.d }, p5/z, [x3, #1, mul vl]
+ldnt1b  { z0.b }, p1/z, [x2, #-5, mul vl]
+ldnt1d  { z3.d }, p4/z, [x5, #-1, mul vl]
+ldnt1h  { z6.h }, p7/z, [x8]
+ldnt1w  { z1.s }, p2/z, [x3, #-8, mul vl]
+ld1rob  { z0.b }, p1/z, [x2]
+ld1rod  { z4.d }, p5/z, [x6, #-0x20]
+ld1roh  { z8.h }, p3/z, [x1, #-0x100]
+ld1row  { z3.s }, p4/z, [x0, #0xE0]
+ld1rqb  { z6.b }, p7/z, [x8, #0x40]
+ld1rqd  { z9.d }, p0/z, [x1, #-0x80]
+ld1rqh  { z4.h }, p5/z, [x6, #0x70]
+ld1rqw  { z3.s }, p2/z, [x1, #-0x10]
+ld2q    { z0.q, z1.q }, p1/z, [x2, #-0x10, mul vl]
+ld2q    { z0.q, z1.q }, p1/z, [x2, #0x0E, mul vl]
+ld3q    { z0.q - z2.q }, p4/z, [x5, #-0x18, mul vl]
+ld3q    { z0.q - z2.q }, p4/z, [x5, #0x15, mul vl]
+ld4q    { z0.q - z3.q }, p5/z, [x3, #-0x20, mul vl]
+ld4q    { z0.q - z3.q }, p5/z, [x3, #0x1C, mul vl]
+ld2q    { z12.q, z13.q }, p1/z, [x2, #-0x10, mul vl]
+ld2q    { z13.q, z14.q }, p1/z, [x2, #0x0E, mul vl]
+ld3q    { z14.q - z16.q }, p4/z, [x5, #-0x18, mul vl]
+ld3q    { z15.q - z17.q }, p4/z, [x5, #0x15, mul vl]
+ld4q    { z16.q - z19.q }, p5/z, [x3, #-0x20, mul vl]
+ld4q    { z27.q - z30.q }, p5/z, [x3, #0x1C, mul vl]
+ld4q    { z28.q - z31.q }, p5/z, [x3, #0x1C, mul vl]
+ld4q    { z29.q, z30.q, z31.q, z0.q }, p5/z, [x3, #0x1C, mul vl]
+ld4q    { z30.q, z31.q, z0.q, z1.q }, p5/z, [x3, #0x1C, mul vl]
+ld4q    { z31.q, z0.q, z1.q, z2.q }, p5/z, [x3, #0x1C, mul vl]
+ld2q    { z31.q, z0.q }, p1/z, [x2, #-0x10, mul vl]
+ld2b    { z0.b, z1.b }, p1/z, [x2, #-0x10, mul vl]
+ld2d    { z4.d, z5.d }, p5/z, [x7, #0x0E, mul vl]
+ld2h    { z6.h, z7.h }, p5/z, [x4, #0x08, mul vl]
+ld2w    { z0.s, z1.s }, p0/z, [x1, #0x02, mul vl]
+ld3b    { z0.b - z2.b }, p0/z, [x0, #0x15, mul vl]
+ld3d    { z0.d - z2.d }, p0/z, [x0, #-0x18, mul vl]
+ld3h    { z0.h - z2.h }, p0/z, [x0, #0x15, mul vl]
+ld3w    { z0.s - z2.s }, p0/z, [x0, #-0x18, mul vl]
+ld4b    { z31.b, z0.b, z1.b, z2.b }, p2/z, [x1, #-0x20, mul vl]
+ld4d    { z8.d - z11.d }, p0/z, [x0, #0x1C, mul vl]
+ld4h    { z5.h - z8.h }, p4/z, [x3, #-0x20, mul vl]
+ld4w    { z0.s - z3.s }, p1/z, [x2, #0x1C, mul vl]
+st2q    { z0.q, z1.q }, p3, [x0, #-0x10, mul vl]
+st3q    { z2.q - z4.q }, p3, [x4, #0x15, mul vl]
+st4q    { z7.q - z10.q }, p6, [x5, #0x1C, mul vl]
+stnt1b  { z1.b }, p2, [x3, #4, mul vl]
+stnt1d  { z8.d }, p7, [x6, #5, mul vl]
+stnt1h  { z9.h }, p1, [x0, #-5, mul vl]
+stnt1w  { z0.s }, p0, [x2, #-7, mul vl]
+st1d    { z1.d }, p2, [x3, #4, mul vl]
+st1w    { z3.q }, p4, [x5, #6, mul vl]
+st1d    { z2.q }, p1, [x0]
+st2b    { z0.b, z1.b }, p1, [x2, #-0x10, mul vl]
+st2d    { z5.d, z6.d }, p4, [x3, #-0x10, mul vl]
+st2h    { z6.h, z7.h }, p7, [x8, #-0x10, mul vl]
+st2w    { z8.s, z9.s }, p1, [x9, #-0x10, mul vl]
+st3b    { z7.b - z9.b }, p6, [x5, #-0x18, mul vl]
+st3d    { z2.d - z4.d }, p3, [x4, #-0x18, mul vl]
+st3h    { z1.h - z3.h }, p2, [x3, #-0x18, mul vl]
+st3w    { z1.s - z3.s }, p3, [x8, #-0x18, mul vl]
+st4b    { z0.b - z3.b }, p0, [x0, #-0x20, mul vl]
+st4d    { z2.d - z5.d }, p0, [x1, #-0x20, mul vl]
+st4h    { z3.h - z6.h }, p5, [x2, #-0x20, mul vl]
+st4w    { z0.s - z3.s }, p1, [x5, #0x1C, mul vl]
\ No newline at end of file

…oup1

ghost · 2023-12-14T01:14:45Z

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

Issue Details

Note: I still have a few more formats to do as well as some cleanup.

Contributes to #94549

Adds the following SVE formats:

Author:	TIHan
Assignees:	TIHan
Labels:	`area-CodeGen-coreclr`
Milestone:	-

kunalspathak

Sorry to take a while to review this.

kunalspathak · 2024-01-09T17:36:30Z

src/coreclr/jit/emitarm64.h

+inline static bool insOptsScalableWordsOrQuadwords(insOpts opt)
+{
+    // `opt` is any of the standard word, quadword and above scalable types.
+    return (insOptsScalableWords(opt) || (opt == INS_OPTS_SCALABLE_Q));


Just a check for INS_OPTS_SCALABLE_Q seems little odd. Probably #96692 would revise this.

That PR would revise this. Should I wait for the PR to be merged then adjust this?

you are adding just 1 entry and since your PR was out for a while now, I would suggest to merge it after you address the feedback.

src/coreclr/jit/emitarm64.cpp

kunalspathak · 2024-01-09T18:11:55Z

src/coreclr/jit/emitarm64.cpp

+        // Therefore, by default return NONE due to ambiguity.
+        case IF_SVE_AH_3A:
+        case IF_SVE_DB_3A:
+            // TODO: Handle these cases.


Need to handle this?

We haven't implemented those formats yet, and also I'm not sure how we will represent <Pg>/<ZM>.

src/coreclr/jit/emitarm64.cpp

src/coreclr/jit/emitarm64.h

kunalspathak · 2024-01-09T18:17:04Z

src/coreclr/jit/emitarm64.cpp

+
+            if (canEncodeSveElemsize_dtype(ins))
+            {
+                code = insEncodeSveElemsize_dtype(ins, optGetSveElemsize(id->idInsOpt()), code);


That could be the reason of TP regression:

src/coreclr/jit/emitarm64.cpp

kunalspathak · 2024-01-09T18:20:54Z

src/coreclr/jit/emitarm64.cpp

-        const bool notLastRegister = (i != listSize - 1);
-        emitDispSveReg(currReg, opt, notLastRegister);
-        currReg = (currReg == REG_V31) ? REG_V0 : REG_NEXT(currReg);
+        if ((listSize == 2) || (((unsigned)currReg + listSize - 1) > (unsigned)REG_V31))


(listSize == 2)

Can't this be true for any listSize > 1?

can you add a unit test that passes REG_V31 and see if they are disassembled correctly?

I already have unit tests that use REG_V31. It prints out ld4b { z31.b, z0.b, z1.b, z2.b }, p2/z, [x1, #-0x20, mul vl], but I may not have one when listsize is 1.

(listSize == 2)

Can't this be true for any listSize > 1?

looks like this is not yet addressed.

Will look at it, I guess we may not need that check.

We do need the check, but I slightly changed it.

kunalspathak · 2024-01-09T18:22:25Z

src/coreclr/jit/emitarm64.cpp

+                    case IF_SVE_JE_3A:
+                    case IF_SVE_JO_3A:
+                        // This does not have to be printed as hex.
+                        // We only do it because the capstone disassembly displays this immediate as hex.


does this work properly with LATEDISASM? Regardless, I would remove the comment about capstone.

I will check

coredistools has trouble decoding some instructions here compared to capstone, so it's going to be different

…oup1

TIHan · 2024-01-09T23:20:31Z

@kunalspathak this is ready again.

capstone left, jit right:

kunalspathak

Looks good, just need to address one outstanding feedback.

src/coreclr/jit/instrsarm64sve.h

kunalspathak · 2024-01-10T14:38:38Z

src/coreclr/jit/emitarm64.cpp

-        const bool notLastRegister = (i != listSize - 1);
-        emitDispSveReg(currReg, opt, notLastRegister);
-        currReg = (currReg == REG_V31) ? REG_V0 : REG_NEXT(currReg);
+        if ((listSize == 2) || (((unsigned)currReg + listSize - 1) > (unsigned)REG_V31))


(listSize == 2)

Can't this be true for any listSize > 1?

looks like this is not yet addressed.

TIHan · 2024-01-10T18:55:24Z

@kunalspathak Ok, addressed the remaining feedback.

kunalspathak · 2024-01-10T19:05:15Z

// We do not want the short-hand for list size of 1 or 2.

Is this true for all the instructions? Currently only sqrshrn uses it and don't think they have a requirement to show the registers using short-hand format: https://docsmirror.github.io/A64/2023-06/sqrshrn_z_mz2.html

I would rewrite it to something like:

assert(listSize > 0);

// We do not want the short-hand for list size of 1 or 2.
if ((listSize <= 2) || (((unsigned)currReg + listSize - 1) > (unsigned)REG_V31))
{
    for (unsigned i = 0; i < listSize; i++)
    {
        const bool notLastRegister = (i != listSize - 1);
        emitDispSveReg(currReg, opt, notLastRegister);
        currReg = (currReg == REG_V31) ? REG_V0 : REG_NEXT(currReg);
    }
}
else
{
    // short-hand. example: { z0.s - z2.s } which is the same as { z0.s, z1.s, z2.s }
    emitDispSveReg(currReg, opt, false);
    printf(" - ");
    emitDispSveReg((regNumber)(currReg + listSize - 1), opt, false);
}

TIHan · 2024-01-10T19:16:37Z

Anything with the syntax { Zn1 - Zn2 } can use the short-hand if it is greater than 2.

TIHan · 2024-01-10T19:18:29Z

@kunalspathak I put in your change.

kunalspathak · 2024-01-10T19:24:31Z

Anything with the syntax { Zn1 - Zn2 } can use the short-hand if it is greater than 2.

Right, but if you see

runtime/src/coreclr/jit/emitarm64.cpp

Line 17433 in 904c439

emitDispSveRegList(id->idReg2(), 2, INS_OPTS_SCALABLE_S, true); // nnnn

, it passes listSize == 2 and with the code in the PR, it will use the short-hand.

I think we should separate the 2 methods, emitDispSveRegList() that just prints the comma separated list and emitDispSveRegListShortHand() that will print the short-hand. Both will have assert(listSize > 1). (sorry, in my suggestion about it should be > 1 rather than 0.

TIHan · 2024-01-10T19:26:34Z

with the code in the PR, it will use the short-hand.

It won't use the short-hand since the list size is 2.

TIHan · 2024-01-10T19:45:03Z

@kunalspathak I renamed emitDispSveRegList to emitDispSveConsecutiveRegList for clarity.

…oup1

kunalspathak

LGTM

TIHan · 2024-01-10T23:53:33Z

Thanks!

…5994)

TIHan added 18 commits December 8, 2023 16:54

Initial work

7251c19

Added another format

bf05a31

Fix-up comment

050ef3b

Added another format

8775968

Added more formats

dc0ab4d

Added more formats

2318532

Merge remote-tracking branch 'upstream/main' into arm64-sve-format-gr…

286448f

…oup1

Properly encoding ld1w

3ebbb3d

Encoding ld1sb properly

0ef3323

Properly encoding ld1b

523a544

Properly encoding ld1sh

08ca147

Properly encoding ld1h

e8aaf87

Fixing up comments

9300110

Simplifying insEncodeSveElemsize_dtype

8233187

Instruction determines how to encode the dtype

224a896

More encodings

1a4a545

More encodings

ab48ede

Added SVE_IQ_3A encoding

a97db1e

ghost assigned TIHan Dec 14, 2023

dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Dec 14, 2023

TIHan mentioned this pull request Dec 14, 2023

Arm64: Implement SVE encodings #94549

Closed

TIHan changed the title ~~JIT: wip ARM64 SVE format encodings, starting at SVE_IH_3A~~ JIT: wip ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A Dec 14, 2023

Merging

8f48c22

TIHan added arm-sve Work related to arm64 SVE/SVE2 support arch-arm64 labels Dec 14, 2023

TIHan added 3 commits December 14, 2023 15:10

Added SVE_IS_3A and SVE_JE_3A formats

6fb3c73

Added SVE_JM_3A format

5e1c2f4

Added SVE_JN_3C, SVE_JN_3C_D and SVE_JO_3A formats

aea7f11

TIHan changed the title ~~JIT: wip ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A~~ JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A Dec 15, 2023

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Rename emitDispSveRegList to emitDispSveConsecutiveRegList

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Test failure - System.NullReferenceException in System.Threading.Lock.TryInitializeStatics #94728

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JIT: ARM64 SVE format encodings, `SVE_IH_3A` to `SVE_JO_3A` #95994

JIT: ARM64 SVE format encodings, `SVE_IH_3A` to `SVE_JO_3A` #95994

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JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994

JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994

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JIT: ARM64 SVE format encodings, `SVE_IH_3A` to `SVE_JO_3A` #95994

JIT: ARM64 SVE format encodings, `SVE_IH_3A` to `SVE_JO_3A` #95994

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