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Arm64: Change regMaskTP to struct #96196

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Arm64: Change regMaskTP to struct #96196

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78e6a5b
wip
kunalspathak Nov 9, 2023
40314a5
Merge remote-tracking branch 'origin/main' into regMask128
kunalspathak Dec 19, 2023
302b4a5
fix all the compilation errors
kunalspathak Dec 19, 2023
3a851ca
Add high field in regMaskTP and use it in popmask
kunalspathak Dec 19, 2023
074199b
Use `high` in all the operators
kunalspathak Dec 19, 2023
69e6d90
fix some crossgen2 errors
kunalspathak Dec 19, 2023
1b27ea2
fix some consecutive register failures
kunalspathak Dec 19, 2023
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43 changes: 39 additions & 4 deletions src/coreclr/jit/compiler.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -167,6 +167,13 @@ inline unsigned genCountBits(uint64_t bits)
return BitOperations::PopCount(bits);
}

#ifdef TARGET_ARM64
inline unsigned genCountBits(regMaskTP mask)
{
return regMaskTP::PopCountRegMask(mask);
}
#endif

/*****************************************************************************
*
* A rather simple routine that counts the number of bits in a given number.
Expand Down Expand Up @@ -874,9 +881,13 @@ inline regNumber genRegNumFromMask(regMaskTP mask)
{
assert(mask != 0); // Must have one bit set, so can't have a mask of zero

/* Convert the mask to a register number */
/* Convert the mask to a register number */

regNumber regNum = (regNumber)genLog2(mask);
#ifdef TARGET_ARM64
regNumber regNum = (regNumber)regMaskTP::BitScanForwardRegMask(mask);
#else
regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
#endif

/* Make sure we got it right */

Expand All @@ -900,9 +911,13 @@ inline regNumber genFirstRegNumFromMaskAndToggle(regMaskTP& mask)
{
assert(mask != 0); // Must have one bit set, so can't have a mask of zero

/* Convert the mask to a register number */
/* Convert the mask to a register number */

#ifdef TARGET_ARM64
regNumber regNum = (regNumber)regMaskTP::BitScanForwardRegMask(mask);
#else
regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
#endif
mask ^= genRegMask(regNum);

return regNum;
Expand All @@ -922,9 +937,13 @@ inline regNumber genFirstRegNumFromMask(regMaskTP mask)
{
assert(mask != 0); // Must have one bit set, so can't have a mask of zero

/* Convert the mask to a register number */
/* Convert the mask to a register number */

#ifdef TARGET_ARM64
regNumber regNum = (regNumber)regMaskTP::BitScanForwardRegMask(mask);
#else
regNumber regNum = (regNumber)BitOperations::BitScanForward(mask);
#endif

return regNum;
}
Expand Down Expand Up @@ -4619,30 +4638,46 @@ inline void* operator new[](size_t sz, Compiler* compiler, CompMemKind cmk)

inline void printRegMask(regMaskTP mask)
{
#ifdef TARGET_ARM64
printf(REG_MASK_ALL_FMT, mask.low);
#else
printf(REG_MASK_ALL_FMT, mask);
#endif
}

inline char* regMaskToString(regMaskTP mask, Compiler* context)
{
const size_t cchRegMask = 24;
char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask.low);
#else
sprintf_s(regmask, cchRegMask, REG_MASK_ALL_FMT, mask);
#endif

return regmask;
}

inline void printRegMaskInt(regMaskTP mask)
{
#ifdef TARGET_ARM64
printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT).low);
#else
printf(REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif
}

inline char* regMaskIntToString(regMaskTP mask, Compiler* context)
{
const size_t cchRegMask = 24;
char* regmask = new (context, CMK_Unknown) char[cchRegMask];

#ifdef TARGET_ARM64
sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT).low);
#else
sprintf_s(regmask, cchRegMask, REG_MASK_INT_FMT, (mask & RBM_ALLINT));
#endif

return regmask;
}
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/jit/gentree.h
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Expand Up @@ -966,7 +966,7 @@ struct GenTree

regMaskSmall gtRsvdRegs; // set of fixed trashed registers

unsigned AvailableTempRegCount(regMaskTP mask = (regMaskTP)-1) const;
unsigned AvailableTempRegCount(regMaskTP mask = static_cast<regMaskTP>(-1)) const;
regNumber GetSingleTempReg(regMaskTP mask = (regMaskTP)-1);
regNumber ExtractTempReg(regMaskTP mask = (regMaskTP)-1);

Expand Down
4 changes: 4 additions & 0 deletions src/coreclr/jit/lsra.cpp
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Expand Up @@ -12595,7 +12595,11 @@ regMaskTP LinearScan::RegisterSelection::select(Interval* currentInterval,
&overallLimitCandidates);
assert(limitConsecutiveResult != RBM_NONE);

#ifdef TARGET_ARM64
unsigned startRegister = regMaskTP::BitScanForwardRegMask(limitConsecutiveResult);
#else
unsigned startRegister = BitOperations::BitScanForward(limitConsecutiveResult);
#endif

regMaskTP registersNeededMask = (1ULL << refPosition->regCount) - 1;
candidates |= (registersNeededMask << startRegister);
Expand Down
4 changes: 2 additions & 2 deletions src/coreclr/jit/lsra.h
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Expand Up @@ -785,8 +785,8 @@ class LinearScan : public LinearScanInterface
static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R3 | RBM_R4 | RBM_R5);
static const regMaskTP LsraLimitSmallFPSet = (RBM_F0 | RBM_F1 | RBM_F2 | RBM_F16 | RBM_F17);
#elif defined(TARGET_ARM64)
static const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
static const regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
const regMaskTP LsraLimitSmallIntSet = (RBM_R0 | RBM_R1 | RBM_R2 | RBM_R19 | RBM_R20);
const regMaskTP LsraLimitSmallFPSet = (RBM_V0 | RBM_V1 | RBM_V2 | RBM_V8 | RBM_V9);
#elif defined(TARGET_X86)
static const regMaskTP LsraLimitSmallIntSet = (RBM_EAX | RBM_ECX | RBM_EDI);
static const regMaskTP LsraLimitSmallFPSet = (RBM_XMM0 | RBM_XMM1 | RBM_XMM2 | RBM_XMM6 | RBM_XMM7);
Expand Down
18 changes: 9 additions & 9 deletions src/coreclr/jit/lsraarm64.cpp
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Expand Up @@ -180,7 +180,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
unsigned int registersNeeded,
regMaskTP* allConsecutiveCandidates)
{
if (BitOperations::PopCount(candidates) < registersNeeded)
if (regMaskTP::PopCountRegMask(candidates) < registersNeeded)
{
// There is no way the register demanded can be satisfied for this RefPosition
// based on the candidates from which it can allocate a register.
Expand All @@ -205,14 +205,14 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
do
{
// From LSB, find the first available register (bit `1`)
regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(currAvailableRegs));
regAvailableStartIndex = regMaskTP::BitScanForwardRegMask(currAvailableRegs);
regMaskTP startMask = (1ULL << regAvailableStartIndex) - 1;

// Mask all the bits that are processed from LSB thru regAvailableStart until the last `1`.
regMaskTP maskProcessed = ~(currAvailableRegs | startMask);

// From regAvailableStart, find the first unavailable register (bit `0`).
if (maskProcessed == RBM_NONE)
if (maskProcessed.low == RBM_NONE)
{
regAvailableEndIndex = 64;
if ((regAvailableEndIndex - regAvailableStartIndex) >= registersNeeded)
Expand All @@ -223,7 +223,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
}
else
{
regAvailableEndIndex = BitOperations::BitScanForward(static_cast<DWORD64>(maskProcessed));
regAvailableEndIndex = regMaskTP::BitScanForwardRegMask(maskProcessed);
}
regMaskTP endMask = (1ULL << regAvailableEndIndex) - 1;

Expand All @@ -234,7 +234,7 @@ regMaskTP LinearScan::filterConsecutiveCandidates(regMaskTP candidates,
AppendConsecutiveMask(regAvailableStartIndex, regAvailableEndIndex, (endMask & ~startMask));
}
currAvailableRegs &= ~endMask;
} while (currAvailableRegs != RBM_NONE);
} while (currAvailableRegs.low != RBM_NONE);

regMaskTP v0_v31_mask = RBM_V0 | RBM_V31;
if ((candidates & v0_v31_mask) == v0_v31_mask)
Expand Down Expand Up @@ -335,7 +335,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
do
{
// From LSB, find the first available register (bit `1`)
regAvailableStartIndex = BitOperations::BitScanForward(static_cast<DWORD64>(unprocessedRegs));
regAvailableStartIndex = regMaskTP::BitScanForwardRegMask(static_cast<DWORD64>(unprocessedRegs));

// For the current range, find how many registers are free vs. busy
regMaskTP maskForCurRange = RBM_NONE;
Expand Down Expand Up @@ -365,12 +365,12 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
maskForCurRange |= (registersNeededMask << regAvailableStartIndex);
maskForCurRange &= m_AvailableRegs;

if (maskForCurRange != RBM_NONE)
if (maskForCurRange.low != RBM_NONE)
{
// In the given range, there are some free registers available. Calculate how many registers
// will need spilling if this range is picked.

int curSpillRegs = registersNeeded - BitOperations::PopCount(maskForCurRange);
int curSpillRegs = registersNeeded - regMaskTP::PopCountRegMask(maskForCurRange);
if (curSpillRegs < maxSpillRegs)
{
consecutiveResultForBusy = 1ULL << regAvailableStartIndex;
Expand All @@ -382,7 +382,7 @@ regMaskTP LinearScan::filterConsecutiveCandidatesForSpill(regMaskTP consecutiveC
}
}
unprocessedRegs &= ~(1ULL << regAvailableStartIndex);
} while (unprocessedRegs != RBM_NONE);
} while (unprocessedRegs.low != RBM_NONE);

// consecutiveResultForBusy should always be a subset of consecutiveCandidates.
assert((consecutiveCandidates & consecutiveResultForBusy) == consecutiveResultForBusy);
Expand Down
7 changes: 7 additions & 0 deletions src/coreclr/jit/lsrabuild.cpp
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Expand Up @@ -2805,6 +2805,13 @@ void LinearScan::buildIntervals()
availableRegCount = REG_INT_COUNT;
}

#if TARGET_ARM64
if ((sizeof(regMaskTP) * 8) > 64)
{
actualRegistersMask = ~RBM_NONE;
}
else
#endif
if (availableRegCount < (sizeof(regMaskTP) * 8))
{
// Mask out the bits that are between 64 ~ availableRegCount
Expand Down
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