Fix: Roll-back v1.2.0 and remove almost flags threshold

dpretet · Apr 18, 2024 · 9172f26 · 9172f26
1 parent fa6f6a0
commit 9172f26
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Showing 4 changed files with 9 additions and 22 deletions.
diff --git a/rtl/async_fifo.v b/rtl/async_fifo.v
@@ -7,16 +7,9 @@
 module async_fifo
 
     #(
-        // Data width
         parameter DSIZE = 8,
-        // Address width
         parameter ASIZE = 4,
-        // Almost full thresold
-        parameter AWFULLSIZE = 1,
-        // Almost empty thresold
-        parameter AREMPTYSIZE = 1,
-        // First word fall-through without latency
-        parameter FALLTHROUGH = "TRUE"
+        parameter FALLTHROUGH = "TRUE" // First word fall-through without latency
     )(
         input  wire             wclk,
         input  wire             wrst_n,
@@ -59,7 +52,7 @@ module async_fifo
 
     // The module handling the write requests
     wptr_full
-    #(ASIZE,AWFULLSIZE)
+    #(ASIZE)
     wptr_full (
     .awfull   (awfull),
     .wfull    (wfull),
@@ -88,7 +81,7 @@ module async_fifo
 
     // The module handling read requests
     rptr_empty
-    #(ASIZE,AREMPTYSIZE)
+    #(ASIZE)
     rptr_empty (
     .arempty  (arempty),
     .rempty   (rempty),

diff --git a/rtl/rptr_empty.v b/rtl/rptr_empty.v
@@ -7,8 +7,7 @@
 module rptr_empty
 
     #(
-    parameter ADDRSIZE = 4,
-    parameter [ADDRSIZE:0]AREMPTYSIZE = 1
+    parameter ADDRSIZE = 4
     )(
     input  wire                rclk,
     input  wire                rrst_n,
@@ -40,7 +39,7 @@ module rptr_empty
     assign raddr     = rbin[ADDRSIZE-1:0];
     assign rbinnext  = rbin + (rinc & ~rempty);
     assign rgraynext = (rbinnext >> 1) ^ rbinnext;
-    assign rgraynextm1 = ((rbinnext + AREMPTYSIZE) >> 1) ^ (rbinnext + AREMPTYSIZE);
+    assign rgraynextm1 = ((rbinnext + 1'b1) >> 1) ^ (rbinnext + 1'b1);
 
     //---------------------------------------------------------------
     // FIFO empty when the next rptr == synchronized wptr or on reset

diff --git a/rtl/wptr_full.v b/rtl/wptr_full.v
@@ -7,8 +7,7 @@
 module wptr_full
 
 	#(
-		parameter ADDRSIZE = 4,
-        parameter [ADDRSIZE:0]AWFULLSIZE = 1
+		parameter ADDRSIZE = 4
 	)(
 		input  wire                wclk,
 		input  wire                wrst_n,
@@ -38,7 +37,7 @@ module wptr_full
     assign waddr = wbin[ADDRSIZE-1:0];
     assign wbinnext  = wbin + (winc & ~wfull);
     assign wgraynext = (wbinnext >> 1) ^ wbinnext;
-    assign wgraynextp1 = ((wbinnext + AWFULLSIZE) >> 1) ^ (wbinnext + AWFULLSIZE);
+    assign wgraynextp1 = ((wbinnext + 1'b1) >> 1) ^ (wbinnext + 1'b1);
 
     //------------------------------------------------------------------
     // Simplified version of the three necessary full-tests:

diff --git a/sim/async_fifo_unit_test.sv b/sim/async_fifo_unit_test.sv
@@ -19,8 +19,6 @@ module async_fifo_unit_test;
 
     parameter DSIZE = 32;
     parameter ASIZE = 4;
-    parameter AREMPTYSIZE = `AEMPTY;
-    parameter AWFULLSIZE = `AFULL;
     parameter FALLTHROUGH = `FALLTHROUGH;
     parameter MAX_TRAFFIC = 10;
 
@@ -43,8 +41,6 @@ module async_fifo_unit_test;
     #(
         .DSIZE        (DSIZE),
         .ASIZE        (ASIZE),
-        .AWFULLSIZE   (AWFULLSIZE),
-        .AREMPTYSIZE  (AREMPTYSIZE),
         .FALLTHROUGH  (FALLTHROUGH)
     )
     dut
@@ -188,7 +184,7 @@ module async_fifo_unit_test;
         `FAIL_IF_NOT_EQUAL(arempty, 0);
 
         winc = 1;
-        for (int i=0; i<AREMPTYSIZE; i=i+1) begin
+        for (int i=0; i<1; i=i+1) begin
 
             @(negedge wclk)
             wdata = i;
@@ -206,7 +202,7 @@ module async_fifo_unit_test;
     `UNIT_TEST("TEST_ALMOST_FULL_FLAG")
 
         winc = 1;
-        for (int i=0; i<2**ASIZE-AWFULLSIZE; i=i+1) begin
+        for (int i=0; i<2**ASIZE-1; i=i+1) begin
 
             @(negedge wclk)
             wdata = i;