Add tss segment selector

dreamos82 · Oct 15, 2023 · 3ba5c0e · 3ba5c0e
1 parent 1a84b4a
commit 3ba5c0e
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Showing 4 changed files with 27 additions and 6 deletions.
diff --git a/src/asm/boot.s b/src/asm/boot.s
@@ -301,9 +301,9 @@ gdt64:
         dq (1 <<44) | (1 << 47) | (1 << 41) | (1 << 43) | (1 << 53) | (3 << 45) ;fourth entry=code=0x18
     .udata equ $ - gdt64
         dq (1 << 44) | (1 << 47) | (1 << 41) | (3 << 45)	;fifth entry = data = 0x20
-    .tss_low equ $ - gdt64
+    .tss_low equ $ - gdt64 ;sixth entry placeholder for TSS entry lower part
         dq 0
-    .tss_high equ $ - gdt64
+    .tss_high equ $ - gdt64 ; seventh entry placeholder for TSS entry higher part
         dq 0
 
 .pointer:

diff --git a/src/include/kernel/x86_64/tss.h b/src/include/kernel/x86_64/tss.h
@@ -10,7 +10,6 @@
 /** This structure is copied from OSDev Notes, Part 6: Userspace.
    * https://github.com/dreamos82/Osdev-Notes/blob/master/06_Userspace/03_Handling_Interrupts.md
    */
-__attribute__((packed))
 struct tss
 {
     uint32_t reserved0;
@@ -28,7 +27,7 @@ struct tss
     uint64_t reserved2;
     uint16_t reserved3;
     uint16_t io_bitmap_offset;
-};
+} __attribute__((packed));
 
 typedef struct tss tss_t;
 

diff --git a/src/kernel/arch/x86_64/cpu/tss.c b/src/kernel/arch/x86_64/cpu/tss.c
@@ -8,7 +8,6 @@ tss_t kernel_tss;
 void initialize_tss(){
 
     loglinef(Verbose, "(%s) Initializing tss", __FUNCTION__);
-    loglinef(Verbose, "(%s) gdt64[0] = 0x%x", __FUNCTION__, gdt64[1]);
 
     // These fields are reserved and must be set to 0
     kernel_tss.reserved0 = 0x0;
@@ -37,5 +36,27 @@ void initialize_tss(){
 }
 
 void load_tss() {
-// TODO
+    // Fields explanation (each entry is 64bit)
+    // TSS_ENTRY_LOW:
+    // 0:15 -> Limit (first 15 bits) should be 0xFFFF
+    // 16:39 -> First 24 bits of kernel_tss address
+    // 40:47 -> Type 4 bits in our case is 1001, 0,  DPL should be 0 , P = 1
+    // 48:55 -> Limit (last 4 bits) can be 0, AVL=available to OS we leave it as 0, 53:54 are 0, 55 G (Granularity)
+    // 55:63 -> Bits 25:31 of the kernel_tss base address
+    // TSS_ENTRY_HIGH
+    // 0:31 -> kernel_tss bits 32:63
+    // 32:63 -> Reserved / 0
+    // TYPE: 1001 (64Bit TSS Available)
+    // BASE_ADDRESS: kernel_tss
+    // LIMIT 16:19 0 DPL: 0 P: 1 G:0
+    gdt64[TSS_ENTRY_LOW] = 0x00;
+    gdt64[TSS_ENTRY_HIGH] = 0x00;
+    gdt64[TSS_ENTRY_LOW] = ((((uint64_t) &kernel_tss>>24) & 0xFF)<<56)  /*bits 56:63*/ | ((uint64_t) (0 & 0xFF) << 48) /* bits 48:55 */ | ((uint64_t)0x89 << 40) /* bits 40:47*/|  ((((uint64_t) &kernel_tss) & 0xFFFFFF) << 16) /* bits 15:39 */ | (uint64_t) 0xFFFF /* Base */;
+    gdt64[TSS_ENTRY_HIGH] = (((uint64_t) &kernel_tss>>32)& 0xFFFFFFFF);
+    loglinef(Verbose, "(%s) Loading TSS Register", __FUNCTION__);
+    loglinef(Verbose, "(%s) kernel_tss address = 0x%x", __FUNCTION__, &kernel_tss);
+    loglinef(Verbose, "(%s) gdt64[4] = 0x%x", __FUNCTION__, (uint64_t)gdt64[TSS_ENTRY_LOW]);
+    loglinef(Verbose, "(%s) gdt64[5] = 0x%x", __FUNCTION__,  (uint64_t)gdt64[TSS_ENTRY_HIGH]);
+
+    //__asm__ __volatile__("ltr %0": :"g" (gdt64[TSS_ENTRY_LOW]));
 }
diff --git a/src/kernel/main.c b/src/kernel/main.c
@@ -171,6 +171,7 @@ void kernel_start(unsigned long addr, unsigned long magic){
     set_irq(KEYBOARD_IRQ, IOREDTBL1, 0x21, 0, 0, false);
     set_irq(PIT_IRQ, IOREDTBL2, 0x22, 0, 0, true);
     initialize_tss();
+    load_tss();
     asm("sti");
 
     uint32_t apic_ticks = calibrate_apic();