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Merge branch 'axxia/soc' into next/soc
Patches from Anders Berg applied individually: Here is version 4 of platform support for AXM5516 SoC. The clk driver is now applied to clk-next. The rest should be ready for arm-soc. Haven't got any response from the power/reset maintainers... I hope this driver can be taken via arm-soc as well. The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15 cores (in a 4x4 cluster configuration). The cores within each cluster share an L2 cache, and the clusters are connected to each other via a CCN-504 cache coherent interconnect. This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located above 4GB in the memory map. * axxia/soc: ARM: dts: axxia: Add reset controller power: reset: Add Axxia system reset driver ARM: axxia: Adding defconfig for AXM55xx ARM: dts: Device tree for AXM55xx. ARM: Add platform support for LSI AXM55xx SoC Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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| Axxia AXM55xx device tree bindings | ||
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| Boards using the AXM55xx SoC need to have the following properties: | ||
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| Required root node property: | ||
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| - compatible = "lsi,axm5516" | ||
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| Boards: | ||
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| LSI AXM5516 Validation board (Amarillo) | ||
| compatible = "lsi,axm5516-amarillo", "lsi,axm5516" |
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Documentation/devicetree/bindings/power_supply/axxia-reset.txt
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| Axxia Restart Driver | ||
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| This driver can do reset of the Axxia SoC. It uses the registers in the syscon | ||
| block to initiate a chip reset. | ||
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| Required Properties: | ||
| -compatible: "lsi,axm55xx-reset" | ||
| -syscon: phandle to the syscon node. | ||
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| Example: | ||
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| syscon: syscon@2010030000 { | ||
| compatible = "lsi,axxia-syscon", "syscon"; | ||
| reg = <0x20 0x10030000 0 0x2000>; | ||
| }; | ||
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| reset: reset@2010031000 { | ||
| compatible = "lsi,axm55xx-reset"; | ||
| syscon = <&syscon>; | ||
| }; |
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| /* | ||
| * arch/arm/boot/dts/axm5516-amarillo.dts | ||
| * | ||
| * Copyright (C) 2013 LSI | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License as published by | ||
| * the Free Software Foundation; either version 2 of the License, or | ||
| * (at your option) any later version. | ||
| */ | ||
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| /dts-v1/; | ||
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| /memreserve/ 0x00000000 0x00400000; | ||
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| #include "axm55xx.dtsi" | ||
| #include "axm5516-cpus.dtsi" | ||
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| / { | ||
| model = "Amarillo AXM5516"; | ||
| compatible = "lsi,axm5516-amarillo", "lsi,axm5516"; | ||
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| memory { | ||
| device_type = "memory"; | ||
| reg = <0 0x00000000 0x02 0x00000000>; | ||
| }; | ||
| }; | ||
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| &serial0 { | ||
| status = "okay"; | ||
| }; | ||
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| &serial1 { | ||
| status = "okay"; | ||
| }; | ||
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| &serial2 { | ||
| status = "okay"; | ||
| }; | ||
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| &serial3 { | ||
| status = "okay"; | ||
| }; | ||
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| &gpio0 { | ||
| status = "okay"; | ||
| }; | ||
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| &gpio1 { | ||
| status = "okay"; | ||
| }; |
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| /* | ||
| * arch/arm/boot/dts/axm5516-cpus.dtsi | ||
| * | ||
| * Copyright (C) 2013 LSI | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License as published by | ||
| * the Free Software Foundation; either version 2 of the License, or | ||
| * (at your option) any later version. | ||
| */ | ||
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| / { | ||
| cpus { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
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| cpu-map { | ||
| cluster0 { | ||
| core0 { | ||
| cpu = <&CPU0>; | ||
| }; | ||
| core1 { | ||
| cpu = <&CPU1>; | ||
| }; | ||
| core2 { | ||
| cpu = <&CPU2>; | ||
| }; | ||
| core3 { | ||
| cpu = <&CPU3>; | ||
| }; | ||
| }; | ||
| cluster1 { | ||
| core0 { | ||
| cpu = <&CPU4>; | ||
| }; | ||
| core1 { | ||
| cpu = <&CPU5>; | ||
| }; | ||
| core2 { | ||
| cpu = <&CPU6>; | ||
| }; | ||
| core3 { | ||
| cpu = <&CPU7>; | ||
| }; | ||
| }; | ||
| cluster2 { | ||
| core0 { | ||
| cpu = <&CPU8>; | ||
| }; | ||
| core1 { | ||
| cpu = <&CPU9>; | ||
| }; | ||
| core2 { | ||
| cpu = <&CPU10>; | ||
| }; | ||
| core3 { | ||
| cpu = <&CPU11>; | ||
| }; | ||
| }; | ||
| cluster3 { | ||
| core0 { | ||
| cpu = <&CPU12>; | ||
| }; | ||
| core1 { | ||
| cpu = <&CPU13>; | ||
| }; | ||
| core2 { | ||
| cpu = <&CPU14>; | ||
| }; | ||
| core3 { | ||
| cpu = <&CPU15>; | ||
| }; | ||
| }; | ||
| }; | ||
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| CPU0: cpu@0 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x00>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU1: cpu@1 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x01>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU2: cpu@2 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x02>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU3: cpu@3 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x03>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU4: cpu@100 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x100>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU5: cpu@101 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x101>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU6: cpu@102 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x102>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU7: cpu@103 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x103>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU8: cpu@200 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x200>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU9: cpu@201 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x201>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU10: cpu@202 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x202>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU11: cpu@203 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x203>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU12: cpu@300 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x300>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU13: cpu@301 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x301>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU14: cpu@302 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x302>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
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| CPU15: cpu@303 { | ||
| device_type = "cpu"; | ||
| compatible = "arm,cortex-a15"; | ||
| reg = <0x303>; | ||
| clock-frequency= <1400000000>; | ||
| cpu-release-addr = <0>; // Fixed by the boot loader | ||
| }; | ||
| }; | ||
| }; |
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