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llvm: Update baseline to f270c9a7d0add028bcb80df5a3d73b85b0ebe7f4
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github-actions[bot] committed Dec 18, 2024
1 parent ac67a2c commit 1a96ce0
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion llvm/llvm-project
Submodule llvm-project updated 31 files
+5 −2 llvm/lib/Analysis/ScalarEvolution.cpp
+19 −13 llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+7 −0 llvm/lib/IR/Constants.cpp
+1 −1 llvm/lib/IR/LLVMContext.cpp
+36 −33 llvm/lib/Target/X86/X86ISelLowering.cpp
+120 −0 llvm/test/Analysis/LoopAccessAnalysis/nusw-predicates.ll
+1 −2 llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-splat-vector.ll
+4 −10 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
+10 −15 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
+4 −10 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
+4 −10 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
+118 −52 llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
+0 −4 llvm/test/CodeGen/AMDGPU/constrained-shift.ll
+677 −935 llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+1 −1 llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
+25 −12 llvm/test/CodeGen/X86/vec_shift6.ll
+2 −2 llvm/test/CodeGen/X86/vector-fshl-sub128.ll
+22 −27 llvm/test/CodeGen/X86/vector-fshr-sub128.ll
+59 −0 llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-A.s
+48 −0 llvm/test/tools/llvm-exegesis/RISCV/latency-by-extension-C.s
+11 −0 llvm/test/tools/llvm-exegesis/RISCV/latency-by-opcode-name-FADD_D.s
+3 −0 llvm/tools/llvm-exegesis/lib/CMakeLists.txt
+15 −3 llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp
+10 −1 llvm/tools/llvm-exegesis/lib/MCInstrDescView.h
+22 −0 llvm/tools/llvm-exegesis/lib/RISCV/CMakeLists.txt
+275 −0 llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+4 −12 llvm/tools/llvm-exegesis/lib/SerialSnippetGenerator.cpp
+6 −4 llvm/tools/llvm-exegesis/lib/SnippetFile.cpp
+11 −1 llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp
+22 −11 llvm/tools/llvm-exegesis/llvm-exegesis.cpp
+4 −7 llvm/utils/TableGen/GlobalISelEmitter.cpp

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