rsz: add corner prefix when design has more than one corner

Signed-off-by: Eder Monteiro <emrmonteiro@precisioninno.com>
eder-matheus · Dec 26, 2024 · d41e22f · d41e22f
1 parent e6f69ae
commit d41e22f
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Showing 6 changed files with 302 additions and 7 deletions.
diff --git a/src/rsz/src/Resizer.i b/src/rsz/src/Resizer.i
@@ -348,13 +348,15 @@ estimate_parasitics_cmd(ParasiticsSrc src, const char* path)
     if (!file_path.empty()) {
       for (Corner* corner : *resizer->getDbNetwork()->corners()) {
         file_path = path;
-        std::string suffix("_");
-        suffix.append(corner->name());
-        if (file_path.find(".spef") != std::string::npos
-            || file_path.find(".SPEF") != std::string::npos) {
-          file_path.insert(file_path.size() - 5, suffix);
-        } else {
-          file_path.append(suffix);
+        if (resizer->getDbNetwork()->corners()->count() > 1) {
+          std::string suffix("_");
+          suffix.append(corner->name());
+          if (file_path.find(".spef") != std::string::npos
+              || file_path.find(".SPEF") != std::string::npos) {
+            file_path.insert(file_path.size() - 5, suffix);
+          } else {
+            file_path.append(suffix);
+          }
         }
 
         std::ofstream* file = new std::ofstream(file_path);

diff --git a/src/rsz/test/CMakeLists.txt b/src/rsz/test/CMakeLists.txt
@@ -24,6 +24,7 @@ or_integration_tests(
     make_parasitics4
     make_parasitics5
     make_parasitics6
+    make_parasitics7
     pin_swap1
     pinswap_flat
     pinswap_hier

diff --git a/src/rsz/test/make_parasitics7.ok b/src/rsz/test/make_parasitics7.ok
@@ -0,0 +1,21 @@
+[INFO ODB-0227] LEF file: Nangate45/Nangate45.lef, created 22 layers, 27 vias, 135 library cells
+[INFO ODB-0128] Design: reg1
+[INFO ODB-0130]     Created 3 pins.
+[INFO ODB-0131]     Created 8 components and 39 component-terminals.
+[INFO ODB-0132]     Created 2 special nets and 16 connections.
+[INFO ODB-0133]     Created 10 nets and 20 connections.
+Net r1q
+ Pin capacitance: 0.83-0.89
+ Wire capacitance: 14.64
+ Total capacitance: 15.47-15.54
+ Number of drivers: 1
+ Number of loads: 1
+ Number of pins: 2
+
+Driver pins
+ r1/Q output (DFF_X1) (103, 201)
+
+Load pins
+ u2/A1 input (AND2_X1) 0.83-0.89 (100, 401)
+
+No differences found.
diff --git a/src/rsz/test/make_parasitics7.spefok b/src/rsz/test/make_parasitics7.spefok
@@ -0,0 +1,122 @@
+*SPEF "ieee 1481-1999"
+*DESIGN "reg1"
+*DATE "11:11:11 Fri 11 11, 1111"
+*VENDOR "The OpenROAD Project"
+*PROGRAM "OpenROAD"
+*VERSION "1.0"
+*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
+*DIVIDER /
+*DELIMITER :
+*BUS_DELIMITER []
+*T_UNIT 1 NS
+*C_UNIT 1 FF
+*R_UNIT 1 KOHM
+*L_UNIT 1 HENRY
+
+*PORTS
+in1 I
+clk I
+out O
+
+*D_NET in1 28.971
+*CONN
+*I r1:D I *D DFF_X1
+*P in1 I
+*I r2:D I *D DFF_X1
+*CAP
+1 in1:0 7.2699
+2 in1:1 3.6078
+3 in1:2 3.6078
+4 in1:3 14.4855
+*RES
+1 in1:0 in1:0 1e-06
+2 in1:0 in1 1e-06
+3 in1:0 in1 1e-06
+4 in1:1 in1:3 0.6516
+5 in1:1 r1:D 1e-06
+6 in1:2 in1:3 0.6516
+7 in1:2 r2:D 1e-06
+8 in1:3 in1:0 1.31301
+9 in1:0 in1 1e-06
+*END
+
+*D_NET out 33.9494
+*CONN
+*P out O
+*I r3:Q O *D DFF_X1
+*CAP
+1 out:0 16.9747
+2 out:1 16.9747
+*RES
+1 out:0 out:1 3.06578
+2 out:0 out 1e-06
+3 out:1 r3:Q 1e-06
+4 out:1 out:1 1e-06
+5 out:1 r3:Q 1e-06
+6 out:1 r3:Q 1e-06
+*END
+
+*D_NET r1q 14.6426
+*CONN
+*I r1:Q O *D DFF_X1
+*I u2:A1 I *D AND2_X1
+*CAP
+1 r1q:0 7.32131
+2 r1q:1 7.32131
+*RES
+1 r1q:0 r1q:1 1.32229
+2 r1q:0 u2:A1 1e-06
+3 r1q:1 r1:Q 1e-06
+4 r1q:1 r1q:1 1e-06
+5 r1q:1 r1:Q 1e-06
+6 r1q:1 r1:Q 1e-06
+*END
+
+*D_NET r2q 14.22
+*CONN
+*I r2:Q O *D DFF_X1
+*I u1:A I *D BUF_X1
+*CAP
+1 r2q:0 7.10998
+2 r2q:1 7.10998
+*RES
+1 r2q:0 r2q:0 1e-06
+2 r2q:0 r2:Q 1e-06
+3 r2q:0 r2:Q 1e-06
+4 r2q:1 r2q:0 1.28412
+5 r2q:1 u1:A 1e-06
+6 r2q:0 r2:Q 1e-06
+*END
+
+*D_NET u1z 43.297
+*CONN
+*I u1:Z O *D BUF_X1
+*I u2:A2 I *D AND2_X1
+*CAP
+1 u1z:0 21.6485
+2 u1z:1 21.6485
+*RES
+1 u1z:0 u1z:1 3.90991
+2 u1z:0 u2:A2 1e-06
+3 u1z:1 u1:Z 1e-06
+4 u1z:1 u1z:1 1e-06
+5 u1z:1 u1:Z 1e-06
+6 u1z:1 u1:Z 1e-06
+*END
+
+*D_NET u2z 21.6713
+*CONN
+*I r3:D I *D DFF_X1
+*I u2:ZN O *D AND2_X1
+*CAP
+1 u2z:0 10.8357
+2 u2z:1 10.8357
+*RES
+1 u2z:0 u2z:0 1e-06
+2 u2z:0 u2:ZN 1e-06
+3 u2z:0 u2:ZN 1e-06
+4 u2z:1 u2z:0 1.95702
+5 u2z:1 r3:D 1e-06
+6 u2z:0 u2:ZN 1e-06
+*END
+
diff --git a/src/rsz/test/make_parasitics7.tcl b/src/rsz/test/make_parasitics7.tcl
@@ -0,0 +1,27 @@
+# 2 corners with set_layer_rc
+source "helpers.tcl"
+define_corners ss
+read_liberty -corner ss Nangate45/Nangate45_slow.lib
+read_lef Nangate45/Nangate45.lef
+read_def reg6.def
+
+create_clock -period 10 clk
+set_input_delay -clock clk 0 in1
+
+# kohm/micron
+set r 5.43e-3
+# fF/micron
+set c 6.013e-2
+
+source Nangate45/Nangate45.rc
+set_layer_rc -layer metal1 -corner ss \
+  -resistance [expr $r * 1.2] -capacitance [expr $c * 1.2]
+set_wire_rc -corner ss -layer metal1
+
+set spef_file [make_result_file make_parasitics7.spef]
+
+estimate_parasitics -placement -spef_file $spef_file
+
+report_net r1/Q -corner ss
+
+diff_file make_parasitics7.spefok $spef_file
diff --git a/src/rsz/test/make_parasitics7_ss.spefok b/src/rsz/test/make_parasitics7_ss.spefok
@@ -0,0 +1,122 @@
+*SPEF "ieee 1481-1999"
+*DESIGN "reg1"
+*DATE "11:11:11 Fri 11 11, 1111"
+*VENDOR "The OpenROAD Project"
+*PROGRAM "OpenROAD"
+*VERSION "1.0"
+*DESIGN_FLOW "NAME_SCOPE LOCAL" "PIN_CAP NONE"
+*DIVIDER /
+*DELIMITER :
+*BUS_DELIMITER []
+*T_UNIT 1 NS
+*C_UNIT 1 FF
+*R_UNIT 1 KOHM
+*L_UNIT 1 HENRY
+
+*PORTS
+in1 I
+clk I
+out O
+
+*D_NET in1 28.971
+*CONN
+*I r1:D I *D DFF_X1
+*P in1 I
+*I r2:D I *D DFF_X1
+*CAP
+1 in1:0 7.2699
+2 in1:1 3.6078
+3 in1:2 3.6078
+4 in1:3 14.4855
+*RES
+1 in1:0 in1:0 1e-06
+2 in1:0 in1 1e-06
+3 in1:0 in1 1e-06
+4 in1:1 in1:3 0.6516
+5 in1:1 r1:D 1e-06
+6 in1:2 in1:3 0.6516
+7 in1:2 r2:D 1e-06
+8 in1:3 in1:0 1.31301
+9 in1:0 in1 1e-06
+*END
+
+*D_NET out 33.9494
+*CONN
+*P out O
+*I r3:Q O *D DFF_X1
+*CAP
+1 out:0 16.9747
+2 out:1 16.9747
+*RES
+1 out:0 out:1 3.06578
+2 out:0 out 1e-06
+3 out:1 r3:Q 1e-06
+4 out:1 out:1 1e-06
+5 out:1 r3:Q 1e-06
+6 out:1 r3:Q 1e-06
+*END
+
+*D_NET r1q 14.6426
+*CONN
+*I r1:Q O *D DFF_X1
+*I u2:A1 I *D AND2_X1
+*CAP
+1 r1q:0 7.32131
+2 r1q:1 7.32131
+*RES
+1 r1q:0 r1q:1 1.32229
+2 r1q:0 u2:A1 1e-06
+3 r1q:1 r1:Q 1e-06
+4 r1q:1 r1q:1 1e-06
+5 r1q:1 r1:Q 1e-06
+6 r1q:1 r1:Q 1e-06
+*END
+
+*D_NET r2q 14.22
+*CONN
+*I r2:Q O *D DFF_X1
+*I u1:A I *D BUF_X1
+*CAP
+1 r2q:0 7.10998
+2 r2q:1 7.10998
+*RES
+1 r2q:0 r2q:0 1e-06
+2 r2q:0 r2:Q 1e-06
+3 r2q:0 r2:Q 1e-06
+4 r2q:1 r2q:0 1.28412
+5 r2q:1 u1:A 1e-06
+6 r2q:0 r2:Q 1e-06
+*END
+
+*D_NET u1z 43.297
+*CONN
+*I u1:Z O *D BUF_X1
+*I u2:A2 I *D AND2_X1
+*CAP
+1 u1z:0 21.6485
+2 u1z:1 21.6485
+*RES
+1 u1z:0 u1z:1 3.90991
+2 u1z:0 u2:A2 1e-06
+3 u1z:1 u1:Z 1e-06
+4 u1z:1 u1z:1 1e-06
+5 u1z:1 u1:Z 1e-06
+6 u1z:1 u1:Z 1e-06
+*END
+
+*D_NET u2z 21.6713
+*CONN
+*I r3:D I *D DFF_X1
+*I u2:ZN O *D AND2_X1
+*CAP
+1 u2z:0 10.8357
+2 u2z:1 10.8357
+*RES
+1 u2z:0 u2z:0 1e-06
+2 u2z:0 u2:ZN 1e-06
+3 u2z:0 u2:ZN 1e-06
+4 u2z:1 u2z:0 1.95702
+5 u2z:1 r3:D 1e-06
+6 u2z:0 u2:ZN 1e-06
+*END
+