Silicon/Rockchip: Add initial DisplayPort support

DwDpLib was ported from U-Boot downstream commit
549d42b6f4d1b261c433c0942868fd6e1b38aaaf.

It has been globally enabled on all RK3588 platforms where DP lanes are exposed.

Output mode is fixed by GOP at 1080p 60Hz - no EDID and HPD implemented yet.

Only works in one orientation of the Type-C connector.

Tested on:
  - R58-Mini (USB-C)
  - Indiedroid Nova (USB-C)
  - ROCK 5A (onboard HDMI -> DP converter)

edk2-rockchip/Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.c

@@ -890,6 +890,7 @@ Vop2CalcCruConfig (
   UINT64 DclkRate = VPixclk;
   UINT64 IfDclkRate;
   UINT64 IfPixclkRate;
+  UINT64 DclkOutRate;
   INT32 OutputType = ConnectorState->Type;
   INT32 OutputMode = ConnectorState->OutputMode;
   UINT8 K = 1;
@@ -939,6 +940,19 @@ Vop2CalcCruConfig (
     *DclkCoreDiv = DclkRate / DclkCoreRate;
     *IfPixclkDiv = DclkRate / IfPixclkRate;
     *IfDclkDiv = *IfPixclkDiv;
+  } else if (OutputType == DRM_MODE_CONNECTOR_DisplayPort) {
+    DclkOutRate = VPixclk >> 2;
+    DclkOutRate = DclkOutRate / K;
+
+    DclkRate = Vop2CalcDclk(DclkOutRate,
+                  Vop2->Data->VpData->MaxDclk);
+    if (!DclkRate) {
+      DEBUG ((DEBUG_ERROR, "DP dclk_core out of range(max_dclk: %d KHZ, dclk_core: %ld KHZ)\n",
+              Vop2->Data->VpData->MaxDclk, DclkCoreRate));
+      return EFI_INVALID_PARAMETER;
+    }
+    *DclkOutDiv = DclkRate / DclkOutRate;
+    *DclkCoreDiv = DclkRate / DclkCoreRate;
   }
 
   *IfPixclkDiv = LogCalculate(*IfPixclkDiv);
@@ -1040,6 +1054,24 @@ Vop2IfConfig (
                   HDMI1_SYNC_POL_SHIFT, Val);
   }
 
+  if (OutputIf & VOP_OUTPUT_IF_DP0) {
+    Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, EN_MASK,
+                    RK3588_DP0_EN_SHIFT, 1, FALSE);
+    Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, IF_MUX_MASK,
+                    RK3588_DP0_MUX_SHIFT, CrtcState->CrtcID, FALSE);
+    Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK,
+                    RK3588_DP0_PIN_POL_SHIFT, Val, FALSE);
+  }
+
+  if (OutputIf & VOP_OUTPUT_IF_DP1) {
+    Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, EN_MASK,
+                    RK3588_DP1_EN_SHIFT, 1, FALSE);
+    Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_EN, IF_MUX_MASK,
+                    RK3588_DP1_MUX_SHIFT, CrtcState->CrtcID, FALSE);
+    Vop2MaskWrite (Vop2->BaseAddress, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK,
+                    RK3588_DP1_PIN_POL_SHIFT, Val, FALSE);
+  }
+
   Vop2MaskWrite (Vop2->BaseAddress, RK3588_VP0_CLK_CTRL + VPOffset, 0x3,
                 DCLK_CORE_DIV_SHIFT, DclkCoreDiv, FALSE);
   Vop2MaskWrite (Vop2->BaseAddress, RK3588_VP0_CLK_CTRL + VPOffset, 0x3,

edk2-rockchip/Silicon/Rockchip/FvMainModules.fdf.inc

@@ -98,6 +98,7 @@
   INF Silicon/Rockchip/Drivers/Vop2Dxe/Vop2Dxe.inf
   # INF Silicon/Rockchip/Library/DisplayLib/AnalogixDpLib.inf
   INF Silicon/Rockchip/Library/DisplayLib/DwHdmiQpLib.inf
+  INF Silicon/Rockchip/Library/DisplayLib/DwDpLib.inf
   INF Silicon/Rockchip/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf
 
   #