[WIP] Caravel on Arty FPGA #12
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…CW_ROOT>/signoff/` add false paths and case analysis reports for top-level caravel STA run
-case analysis for the 38 IO pads -false path from some pads inputs to the housekeeping
update signoff scripts
like avoid obstructions in the padframe and power routing, add decap, and separate coupling wires to reduce capacitance.
Mgmt protect without labeles
Corrected one instance where a buffer had incorrectly been replaced with a decap cell. Moved the left-hand side in by 0.6um to clear the chip_io connections on the left-hand side. Corrected a small DRC error in a route position at the bottom.
- based on second iteration of the buffer macro - change config with updated placement of spare logic macros and power routing cell
…nto fix_top_buffers_again
Updating to the most recent caravel_redesign branch version.
above housekeeping, because the upper GPIO pins are in the wrong place relative to the new GPIO signal routing below the SoC. Added pins for the pass-through connections. Unconnected/ unrouted OEB pins are still not present and probably should be removed from the RTL.
…nto fix_top_buffers_again
being buffered pass through the buffer macros. Removed the straight-through signals from the layout, and renumbered the vectors in the buffer cells, which no longer match the numbering at the top level (unfortunately).
This reverts commit 61d1f23.
…nto fix_top_buffers_again
abstract caravan.spice
Caravel fails to build with recent Icarus Verilog versions because some of the port definitions are not valid.
Fix issues with port definitions
Update serial configuration fsm to reset the transfer bit
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
Signed-off-by: Rafal Kolucki <rkolucki@antmicro.com>
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@tmichalak awesome! How many LUTs does it use? |
@proppy currently it takes ~4K LUTs. It is still missing few things, like the clock control - the DLL needs to be replaced with a Xilinx PLL primitive and some FSM to enable control though the housekeeping module |
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This PR adds initial support for building the caravel design for an Arty FPGA.
The design uses the updated version of the mgmt_core see PR
Currently the SKY130 macros were replaced matching Xilinx equivalents or generic Verilog code.
The design is clocked from an external clock (the DLL needs to be replaced with a Xilinx PLL primitive and some FSM to enable control through the housekeeping module).
Added a
vivadotarget to the Makefile in order to build the bitstream.