Representing Loops within Egg #106
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I'm really struggling to figure out how to express more advanced control flow with egg, things like |
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The original paper on equality saturation (https://www.cs.cornell.edu/~ross/publications/eqsat/) features loops, I would assume that you can re-use the same loop representation technique with egg? |
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I'm grateful that you mentioned RVSDG here, @Kixiron. Based on your suggestion I read those papers this month, especially "Perfect Reconstructability of Control Flow from Demand Dependence Graphs", which convinced me that it's a good model for arbitrary control flow in an e-graph. Re-reading my own blog post from five years ago ("Search-based compiler code generation"), I'd apparently discovered the "Perfect Reconstructability" paper then, but by the time I learned about equality saturation I'd forgotten all about it. And now I have a working prototype of e-graphs for RVSDG, based on egg. Every valid RVSDG is acyclic, so avoids the extraction difficulties discussed here, but you can still round-trip even irreducible control flow through it. I'm very pleased both with egg and with how this experiment has turned out. And yes, to the original question, loops seem to work fine in this model. |
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I'm grateful that you mentioned RVSDG here, @Kixiron. Based on your suggestion I read those papers this month, especially "Perfect Reconstructability of Control Flow from Demand Dependence Graphs", which convinced me that it's a good model for arbitrary control flow in an e-graph. Re-reading my own blog post from five years ago ("Search-based compiler code generation"), I'd apparently discovered the "Perfect Reconstructability" paper then, but by the time I learned about equality saturation I'd forgotten all about it.
And now I have a working prototype of e-graphs for RVSDG, based on egg. Every valid RVSDG is acyclic, so avoids the extraction difficulties discussed here, but you can still…