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Jan 21, 2023
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178 changes: 5 additions & 173 deletions Cargo.lock

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2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@ notify = "5.0.0"
object = { version = "0.30.2", features = ["read_core", "std", "elf"], default-features = false }
png = "0.17.7"
ppc750cl = { git = "https://github.com/terorie/ppc750cl", rev = "9ae36eef34aa6d74e00972c7671f547a2acfd0aa" }
rabbitizer = { git = "https://github.com/encounter/rabbitizer-rs", rev = "10c279b2ef251c62885b1dcdcfe740b0db8e9956" }
rabbitizer = "1.5.7"
rfd = { version = "0.10.0" } #, default-features = false, features = ['xdg-portal']
serde = { version = "1", features = ["derive"] }
tempfile = "3.3.0"
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30 changes: 18 additions & 12 deletions src/obj/mips.rs
Original file line number Diff line number Diff line change
@@ -1,18 +1,24 @@
use std::collections::BTreeMap;

use anyhow::Result;
use rabbitizer::{config_set_register_fpr_abi_names, Abi, Instruction, SimpleOperandType};
use rabbitizer::{config, Abi, Instruction, InstrCategory, OperandType};

use crate::obj::{ObjIns, ObjInsArg, ObjReloc};

fn configure_rabbitizer() {
unsafe {
config::RabbitizerConfig_Cfg.reg_names.fpr_abi_names = Abi::O32;
}
}

pub fn process_code(
data: &[u8],
start_address: u64,
end_address: u64,
relocs: &[ObjReloc],
line_info: &Option<BTreeMap<u32, u32>>,
) -> Result<(Vec<u8>, Vec<ObjIns>)> {
config_set_register_fpr_abi_names(Abi::RABBITIZER_ABI_O32);
configure_rabbitizer();

let ins_count = data.len() / 4;
let mut ops = Vec::<u8>::with_capacity(ins_count);
Expand All @@ -21,21 +27,21 @@ pub fn process_code(
for chunk in data.chunks_exact(4) {
let reloc = relocs.iter().find(|r| (r.address as u32 & !3) == cur_addr);
let code = u32::from_be_bytes(chunk.try_into()?);
let mut instruction = Instruction::new(code, cur_addr);
let instruction = Instruction::new(code, cur_addr, InstrCategory::CPU);

let op = instruction.instr_id() as u8;
let op = instruction.unique_id as u8;
ops.push(op);

let mnemonic = instruction.instr_id().get_opcode_name().unwrap_or_default().to_string();
let mnemonic = instruction.opcode_name().to_string();
let is_branch = instruction.is_branch();
let branch_offset = instruction.branch_offset();
let branch_dest =
if is_branch { Some((cur_addr as i32 + branch_offset) as u32) } else { None };
let args = instruction
.simple_operands()
.get_operands_slice()
.iter()
.map(|op| match op.kind {
SimpleOperandType::Imm | SimpleOperandType::Label => {
.map(|op| match op {
OperandType::cpu_immediate | OperandType::cpu_label | OperandType::cpu_branch_target_label => {
if is_branch {
ObjInsArg::BranchOffset(branch_offset)
} else if let Some(reloc) = reloc {
Expand All @@ -49,17 +55,17 @@ pub fn process_code(
ObjInsArg::Reloc
}
} else {
ObjInsArg::MipsArg(op.disassembled.clone())
ObjInsArg::MipsArg(op.disassemble(&instruction, None))
}
}
SimpleOperandType::ImmBase => {
OperandType::cpu_immediate_base => {
if reloc.is_some() {
ObjInsArg::RelocWithBase
} else {
ObjInsArg::MipsArg(op.disassembled.clone())
ObjInsArg::MipsArg(op.disassemble(&instruction, None))
}
}
_ => ObjInsArg::MipsArg(op.disassembled.clone()),
_ => ObjInsArg::MipsArg(op.disassemble(&instruction, None)),
})
.collect();
let line =
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