frontend/axi: add assertion on matching axi, native port data_width

enjoy-digital · Oct 23, 2019 · 24203cf · 24203cf
1 parent d84e1b4
commit 24203cf
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/litedram/frontend/axi.py b/litedram/frontend/axi.py
@@ -32,6 +32,7 @@ class LiteDRAMAXIPort(AXIInterface):
 class LiteDRAMAXI2NativeW(Module):
     def __init__(self, axi, port, buffer_depth, base_address):
         assert axi.address_width >= log2_int(base_address)
+        assert axi.data_width == port.data_width
         self.cmd_request = Signal()
         self.cmd_grant = Signal()
 
@@ -99,6 +100,7 @@ def __init__(self, axi, port, buffer_depth, base_address):
 class LiteDRAMAXI2NativeR(Module):
     def __init__(self, axi, port, buffer_depth, base_address):
         assert axi.address_width >= log2_int(base_address)
+        assert axi.data_width == port.data_width
         self.cmd_request = Signal()
         self.cmd_grant = Signal()