gen: fix LiteDRAMFIFO parameters

enjoy-digital · Jun 3, 2020 · e5179eb · e5179eb
1 parent 8fedc3f
commit e5179eb
Showing 1 changed file with 0 additions and 2 deletions.
diff --git a/litedram/gen.py b/litedram/gen.py
@@ -609,9 +609,7 @@ def __init__(self, platform, core_config, **kwargs):
                     base            = port["base"],
                     depth           = port["depth"],
                     write_port      = self.sdram.crossbar.get_port("write"),
-                    write_threshold = port["depth"] - 32, # FIXME
                     read_port       = self.sdram.crossbar.get_port("read"),
-                    read_threshold  = 32 # FIXME
                 )
                 self.submodules += fifo
                 self.comb += [