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Issues: enjoy-digital/liteeth

Feedback / Contribution / Support
#44 opened Aug 3, 2020 by enjoy-digital
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23 Open 43 Closed
23 Open 43 Closed
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Issues list

Performance drop when adding packetizer
#170 opened Sep 15, 2024 by wnagele
2
Updating liteeth PyPI package?
#159 opened Apr 9, 2024 by fischermoseley
10
mdio writes in udp config
#156 opened Feb 15, 2024 by ameetgohil
1
Packets are not received
#154 opened Jan 22, 2024 by JochiSt
Liteeth does not transmit out UDP packets with length 16
#152 opened Nov 12, 2023 by rowanG077
3
Question : Compatibility with XC7S25 Spartan-7 for SGMII core
#150 opened Oct 25, 2023 by PJfixer
3
HSGMII/QSGMII PHYs support for 2.5GBASE-T/5GBASE-T
#144 opened Aug 21, 2023 by ohault
ARP table improvements
#140 opened Jul 20, 2023 by rowanG077
LiteEthPHYMII vs LiteEthPHYGMII question
#131 opened Apr 6, 2023 by roryt12
Is it possible to generate generic Liteeth Verilog?
#130 opened Mar 14, 2023 by PedroAntunes178
1
When liteeth core is under reset it transmit out stale packets
#129 opened Mar 2, 2023 by rowanG077
1
empty UDP packets and with content larger then 1472 bytes crashes core
#128 opened Feb 19, 2023 by rowanG077
Custom RMII PHY PMOD question
#125 opened Jan 3, 2023 by machdyne
2
Add options to set link speed and duplex status manually new-feature
#109 opened May 16, 2022 by romanetz
Request for info about daisy-chaining 5a75b boards with etherbone new-feature question
#103 opened Feb 25, 2022 by faeboli
8
CI/Doc: Add tests for 32-bit/64-bit Datapath. guide
#89 opened Nov 1, 2021 by enjoy-digital
2
Regression with Etherbone/LiteScope and PacketFIFO? regression
#86 opened Oct 20, 2021 by enjoy-digital
6
Sending ethernet frames using software question
#68 opened May 25, 2021 by BD00ley
1
linux driver polling mode not init bug? question
#62 opened Feb 18, 2021 by Chgavilana
1
LiteEth Linux driver: Discuss software interface, make sure it's convenient and will be stable over time. enhancement help wanted
#60 opened Feb 9, 2021 by enjoy-digital
2
Feedback / Contribution / Support guide
#44 opened Aug 3, 2020 by enjoy-digital
phy/usrgmii.py: IDELAY_VALUE cannot exceed 1.25ns for Xilinx Ultrascale Devices. enhancement
#29 opened Jan 29, 2020 by jersey99
@enjoy-digital
ECP5 / RGMII doesn't meet timing closure enhancement
#27 opened Jan 25, 2020 by ximinity
14
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