serdes/gty_ultrascale_init: Add DRP support.

liteiclink/serdes/gty_ultrascale_init.py

@@ -7,9 +7,10 @@
 from math import ceil
 
 from migen import *
+from migen.genlib.cdc import MultiReg
 
 from litex.gen import *
-from litex.gen.genlib.cdc import MultiReg
+
 from litex.gen.genlib.misc import WaitTimer
 
 
@@ -33,6 +34,10 @@ def __init__(self, sys_clk_freq, rx, buffer_enable):
         self.Xxsyncdone      = Signal() # i
         self.Xxuserrdy       = Signal() # o
 
+        # DRP (optional)
+        self.drp_start       = Signal()        # o
+        self.drp_done        = Signal(reset=1) # i
+
         # # #
 
         # Double-latch transceiver asynch outputs
@@ -67,7 +72,7 @@ def __init__(self, sys_clk_freq, rx, buffer_enable):
         self.fsm = fsm = ResetInserter()(FSM(reset_state="RESET_ALL"))
 
         ready_timer = WaitTimer(10e-3*sys_clk_freq)
-        self.submodules += ready_timer
+        self.ready_timer = ready_timer
         self.comb += [
             ready_timer.wait.eq(~self.done & ~fsm.reset),
             fsm.reset.eq(self.restart | ready_timer.done)
@@ -87,6 +92,14 @@ def __init__(self, sys_clk_freq, rx, buffer_enable):
             self.pllreset.eq(1),
             pll_reset_timer.wait.eq(1),
             If(pll_reset_timer.done,
+                NextState("DRP")
+            )
+        )
+        fsm.act("DRP",
+            gtXxreset.eq(1),
+            self.pllreset.eq(1),
+            self.drp_start.eq(1),
+            If(self.drp_done,
                 NextState("RELEASE_PLL_RESET")
             )
         )