serwb/phy: List supported FPGA families and add support for all Xilin…

…x Ultrascale(+) and 7-Series.

liteiclink/serwb/phy.py

@@ -404,21 +404,30 @@ def __init__(self, device, pads, mode="master", init_timeout=2**16, clk="sys", c
 
         # SerDes.
         # -------
-        if device[:4] == "xcku":
+
+        # Xilinx Ultrascale(+).
+        if device[:4] in ["xcku", "xvu", "xczu"]:
             assert clk_ratio == "1:1"
             taps = 512
             self.serdes = KUSerdes(pads, mode)
-        elif device[:4] in ["xc7a", "xc7z"]:
+
+        # Xilinx 7-Series.
+        elif device[:4] in ["xc7a", "xc7k", "xc7v", "xc7z"]:
             assert clk_ratio == "1:1"
             taps = 32
             self.serdes = S7Serdes(pads, mode)
+
+
+        # Efinix Titanium.
         elif device[:2] == "Ti":
             taps = 64
             self.serdes = EfinixSerdes(pads, mode,
                 clk       = clk,
                 clk4x     = clk4x,
                 clk_ratio = clk_ratio,
             )
+
+        # Efinix Trion.
         elif device[:2] in ["T1", "T2"]:
             taps = 4 # No dynamic delay
             self.serdes = EfinixSerdes(pads, mode,