liteiclink/serdes/common: Add DRPControl module to access DRP interfa…

…ce from SoC or over the different XYBone.

Useful to easily dump primitive internal configuration/registers.

liteiclink/serdes/common.py

@@ -8,6 +8,8 @@
 
 from litex.gen import *
 
+from litex.soc.interconnect.csr import *
+
 # DRP Layout ---------------------------------------------------------------------------------------
 
 _drp_layout = [
@@ -46,3 +48,43 @@ def do_finalize(self):
         for i, interface in enumerate(self.interfaces):
             cases[i] = interface.connect(self)
         self.comb += Case(self.sel, cases)
+
+# DRP Control --------------------------------------------------------------------------------------
+
+class DRPControl(LiteXModule):
+    def __init__(self, drp):
+        self._addr  = CSRStorage(9,  description="DRP Address (9 bits).")
+        self._di    = CSRStorage(16, description="DRP Data In (16 bits) for write operation.")
+        self._do    = CSRStatus(16,  description="DRP Data Out (16 bits) for read operation.")
+        self._we    = CSRStorage(1,  description="DRP Write Enable.")
+        self._start = CSRStorage(1,  description="Write to initiate DRP operation.")
+        self._done  = CSRStatus(1,   description="DRP operation is complete.")
+
+        # # #
+
+        # Clk.
+        self.comb += drp.clk.eq(ClockSignal("sys"))
+
+        # FSM.
+        self.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
+        self.comb += fsm.reset.eq(self._start.re)
+
+        fsm.act("IDLE",
+            NextState("ACCESS")
+        )
+        fsm.act("ACCESS",
+            drp.en.eq(1),
+            drp.we.eq(self._we.storage),
+            drp.addr.eq(self._addr.storage),
+            drp.di.eq(self._di.storage),
+            NextState("WAIT")
+        )
+        fsm.act("WAIT",
+            If(drp.rdy,
+                NextValue(self._do.status, drp.do),
+                NextState("DONE")
+            )
+        )
+        fsm.act("DONE",
+            self._done.status.eq(1)
+        )