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examples: improve presentation/readability
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@enjoy-digital
enjoy-digital committed Dec 2, 2019
1 parent 8b9e1fd commit a41508e
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19 changes: 12 additions & 7 deletions examples/targets/bist.py
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@
from litesata.frontend.arbitration import LiteSATACrossbar
from litesata.frontend.bist import LiteSATABIST

# CRG ----------------------------------------------------------------------------------------------

class CRG(Module):
def __init__(self, platform):
Expand All @@ -30,6 +31,7 @@ def __init__(self, platform):
pll.register_clkin(clk200, 200e6)
pll.create_clkout(self.cd_sys, 200e6)

# StatusLeds ---------------------------------------------------------------------------------------

class StatusLeds(Module):
def __init__(self, platform, sata_phys):
Expand Down Expand Up @@ -58,6 +60,7 @@ def __init__(self, platform, sata_phys):
# ready leds
self.comb += platform.request("user_led", 2*i+1).eq(sata_phy.ctrl.ready)

# BISTSoC ------------------------------------------------------------------------------------------

class BISTSoC(SoCMini):
default_platform = "kc705"
Expand All @@ -71,24 +74,27 @@ def __init__(self, platform, revision="sata_gen3", data_width=16):
csr_data_width = 32,
ident = "LiteSATA example design",
ident_version = True)

# Serial Bridge ----------------------------------------------------------------------------
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
self.submodules.crg = CRG(platform)

# SATA PHY/Core/Frontend
# SATA PHY/Core/Frontend -------------------------------------------------------------------
self.submodules.sata_phy = LiteSATAPHY(platform.device,
platform.request("sata_clocks"),
platform.request("sata", 0),
revision,
clk_freq,
data_width)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)

# Status Leds
# Status Leds ------------------------------------------------------------------------------
self.submodules.leds = StatusLeds(platform, self.sata_phy)

# Timing constraints -----------------------------------------------------------------------
self.sata_phy.crg.cd_sata_rx.clk.attr.add("keep")
self.sata_phy.crg.cd_sata_tx.clk.attr.add("keep")
platform.add_platform_command("""
Expand All @@ -103,6 +109,8 @@ def __init__(self, platform, revision="sata_gen3", data_width=16):
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
""".format(sata_clk_period="3.3" if data_width == 16 else "6.6"))

# BISTSoCDevel -------------------------------------------------------------------------------------

class BISTSoCDevel(BISTSoC):
csr_map = {
"analyzer": 17
Expand All @@ -111,8 +119,6 @@ class BISTSoCDevel(BISTSoC):
def __init__(self, platform):
from litescope import LiteScopeAnalyzer
BISTSoC.__init__(self, platform)

# analyzer signals
analyzer_signals = [
self.sata_phy.ctrl.ready,
self.sata_phy.source,
Expand All @@ -128,7 +134,6 @@ def __init__(self, platform):
self.sata_core.command.rx.fsm,
self.sata_core.command.tx.fsm,
]

self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 2048, csr_csv="test/analyzer.csv")

default_subtarget = BISTSoC
30 changes: 18 additions & 12 deletions examples/targets/bist_nexys_video.py
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Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@
from litesata.frontend.arbitration import LiteSATACrossbar
from litesata.frontend.bist import LiteSATABIST

# CRG ----------------------------------------------------------------------------------------------

class CRG(Module):
def __init__(self, platform):
Expand All @@ -30,6 +31,7 @@ def __init__(self, platform):
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, 100e6)

# StatusLeds ---------------------------------------------------------------------------------------

class StatusLeds(Module):
def __init__(self, platform, sata_phys):
Expand Down Expand Up @@ -82,6 +84,8 @@ def __init__(self, platform, sata_phys):
self.comb += platform.request("user_led", 4*i+3).eq(sata_phy.ctrl.ready)


# BISTSoC ------------------------------------------------------------------------------------------

class BISTSoC(SoCMini):
default_platform = "kc705"
csr_map = {
Expand All @@ -94,24 +98,27 @@ def __init__(self, platform, revision="sata_gen2", data_width=16):
csr_data_width = 32,
ident = "LiteSATA example design",
ident_version = True)

# Serial Bridge ----------------------------------------------------------------------------
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
self.submodules.crg = CRG(platform)

# SATA PHY/Core/Frontend
# SATA PHY/Core/Frontend -------------------------------------------------------------------
self.submodules.sata_phy = LiteSATAPHY(platform.device,
platform.request("sata_clocks"),
platform.request("sata", 0),
revision,
sys_clk_freq,
data_width)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
platform.request("sata_clocks"),
platform.request("sata", 0),
revision,
sys_clk_freq,
data_width)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)

# Status Leds
# Status Leds ------------------------------------------------------------------------------
self.submodules.leds = StatusLeds(platform, self.sata_phy)

# Timing constraints -----------------------------------------------------------------------
self.sata_phy.crg.cd_sata_rx.clk.attr.add("keep")
self.sata_phy.crg.cd_sata_tx.clk.attr.add("keep")
platform.add_platform_command("""
Expand All @@ -126,6 +133,8 @@ def __init__(self, platform, revision="sata_gen2", data_width=16):
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
""".format(sata_clk_period="6.6" if data_width == 16 else "13.2"))

# BISTSoCDevel -------------------------------------------------------------------------------------

class BISTSoCDevel(BISTSoC):
csr_map = {
"analyzer": 17
Expand All @@ -134,8 +143,6 @@ class BISTSoCDevel(BISTSoC):
def __init__(self, platform):
from litescope import LiteScopeAnalyzer
BISTSoC.__init__(self, platform)

# analyzer signals
analyzer_signals = [
self.sata_phy.crg.tx_startup_fsm,
self.sata_phy.crg.rx_startup_fsm,
Expand All @@ -153,7 +160,6 @@ def __init__(self, platform):
self.sata_core.command.rx.fsm,
self.sata_core.command.tx.fsm,
]

self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 256, csr_csv="test/analyzer.csv")

default_subtarget = BISTSoCDevel
39 changes: 24 additions & 15 deletions examples/targets/core.py
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
# This file is Copyright (c) 2015-2018 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD

from migen.genlib.resetsync import AsyncResetSynchronizer
Expand All @@ -15,6 +15,7 @@
from litesata.frontend.raid import LiteSATAStriping
from litesata.frontend.bist import LiteSATABIST

# IOs ----------------------------------------------------------------------------------------------

_io = [
("sys_clock", 0, Pins(1)),
Expand Down Expand Up @@ -89,12 +90,15 @@
Subsignal("source_write", Pins(1)),
Subsignal("source_read", Pins(1)),
Subsignal("source_identify", Pins(1)),
Subsignal("source_end", Pins(1)),
Subsignal("source_end", Pins(1)),
Subsignal("source_failed", Pins(1)),
Subsignal("source_data", Pins(128)), #FIXME
),
]


# Platform -----------------------------------------------------------------------------------------

class CorePlatform(XilinxPlatform):
name = "core"
def __init__(self):
Expand All @@ -103,6 +107,7 @@ def __init__(self):
def do_finalize(self, *args, **kwargs):
pass

# Core ---------------------------------------------------------------------------------------------

class Core(Module):
platform = CorePlatform()
Expand All @@ -116,16 +121,20 @@ def __init__(self, platform, design="base", clk_freq=200*1000000, nports=1, port
]

if design == "base" or design == "bist":
# SATA PHY/Core/frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata"), "sata_gen3", clk_freq)
self.sata_phys = [self.sata_phy]
self.submodules.sata_core = LiteSATACore(self.sata_phy)
# SATA PHY/Core/frontend ---------------------------------------------------------------
self.submodules.sata_phy = LiteSATAPHY(platform.device,
platform.request("sata_clocks"),
platform.request("sata"),
"sata_gen3",
clk_freq)
self.sata_phys = [self.sata_phy]
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)

if design == "bist":
# BIST
# BIST -----------------------------------------------------------------------------
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar)
generator = self.sata_bist.generator
generator = self.sata_bist.generator
generator_pads = platform.request("generator")
self.comb += [
generator.start.eq(generator_pads.start),
Expand All @@ -138,7 +147,7 @@ def __init__(self, platform, design="base", clk_freq=200*1000000, nports=1, port
generator_pads.errors.eq(generator.errors)
]

checker = self.sata_bist.checker
checker = self.sata_bist.checker
checker_pads = platform.request("checker")
self.comb += [
checker.start.eq(checker_pads.start),
Expand All @@ -151,7 +160,7 @@ def __init__(self, platform, design="base", clk_freq=200*1000000, nports=1, port
checker_pads.errors.eq(checker.errors),
]

identify = self.sata_bist.identify
identify = self.sata_bist.identify
identify_pads = platform.request("identify")
self.comb += [
identify.start.eq(identify_pads.start),
Expand All @@ -167,7 +176,7 @@ def __init__(self, platform, design="base", clk_freq=200*1000000, nports=1, port

elif design == "striping":
self.nphys = 4
# SATA PHYs
# SATA PHYs ----------------------------------------------------------------------------
self.sata_phys = []
for i in range(self.nphys):
sata_phy = LiteSATAPHY(platform.device,
Expand All @@ -180,14 +189,14 @@ def __init__(self, platform, design="base", clk_freq=200*1000000, nports=1, port
setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)
self.sata_phys.append(sata_phy)

# SATA Cores
# SATA Cores ---------------------------------------------------------------------------
self.sata_cores = []
for i in range(self.nphys):
sata_core = LiteSATACore(self.sata_phys[i])
setattr(self.submodules, "sata_core{}".format(str(i)), sata_core)
self.sata_cores.append(sata_core)

# SATA Frontend
# SATA Frontend ------------------------------------------------------------------------
self.submodules.sata_striping = LiteSATAStriping(self.sata_cores)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_striping)

Expand All @@ -199,7 +208,7 @@ def __init__(self, platform, design="base", clk_freq=200*1000000, nports=1, port
ValueError("Unknown design " + design)


# CRG / Ctrl ready
# CRG / Ctrl ready -------------------------------------------------------------------------
crg_ready_pads = platform.request("crg_ready")
ctrl_ready_pads = platform.request("ctrl_ready")
for i, sata_phy in enumerate(self.sata_phys):
Expand All @@ -208,7 +217,7 @@ def __init__(self, platform, design="base", clk_freq=200*1000000, nports=1, port
ctrl_ready_pads[i].eq(sata_phy.ctrl.ready)
]

# Get user ports from crossbar
# Get user ports from crossbar -------------------------------------------------------------
self.user_ports = self.sata_crossbar.get_ports(nports, ports_dw)
for i, user_port in enumerate(self.user_ports):
user_port_pads = platform.request("user_port", i+1)
Expand Down
25 changes: 14 additions & 11 deletions examples/targets/mirroring.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@

from targets.bist import CRG, StatusLeds

# MirroringSoC -------------------------------------------------------------------------------------

class MirroringSoC(SoCMini):
default_platform = "kc705"
Expand All @@ -33,50 +34,52 @@ def __init__(self, platform, revision="sata_gen3", data_width=16, nphys=4):
csr_data_width = 32,
ident = "LiteSATA example design",
ident_version = True)

# Serial Bridge ----------------------------------------------------------------------------
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
self.submodules.crg = CRG(platform)

# SATA PHYs
# SATA PHYs --------------------------------------------------------------------------------
self.sata_phys = []
for i in range(self.nphys):
sata_phy = LiteSATAPHY(platform.device,
platform.request("sata_clocks") if i == 0 else self.sata_phys[0].crg.refclk,
platform.request("sata", i),
revision,
clk_freq,
data_width)
platform.request("sata_clocks") if i == 0 else self.sata_phys[0].crg.refclk,
platform.request("sata", i),
revision,
clk_freq,
data_width)
sata_phy = ClockDomainsRenamer({"sata_rx": "sata_rx{}".format(str(i)),
"sata_tx": "sata_tx{}".format(str(i))})(sata_phy)
setattr(self.submodules, "sata_phy{}".format(str(i)), sata_phy)
self.sata_phys.append(sata_phy)

# SATA Cores
# SATA Cores -------------------------------------------------------------------------------
self.sata_cores = []
for i in range(self.nphys):
sata_core = LiteSATACore(self.sata_phys[i])
setattr(self.submodules, "sata_core{}".format(str(i)), sata_core)
self.sata_cores.append(sata_core)

# SATA Frontend
# SATA Frontend ----------------------------------------------------------------------------
self.submodules.sata_mirroring = LiteSATAMirroring(self.sata_cores)
self.sata_crossbars = []
for i in range(self.nphys):
sata_crossbar = LiteSATACrossbar(self.sata_mirroring.ports[i])
setattr(self.submodules, "sata_crossbar{}".format(str(i)), sata_crossbar)
self.sata_crossbars.append(sata_crossbar)

# SATA Application
# SATA Application -------------------------------------------------------------------------
self.sata_bists = []
for i in range(self.nphys):
sata_bist = LiteSATABIST(self.sata_crossbars[i], with_csr=True)
setattr(self.submodules, "sata_bist{}".format(str(i)), sata_bist)
self.sata_bists.append(sata_bist)

# Status Leds
# Status Leds ------------------------------------------------------------------------------
self.submodules.status_leds = StatusLeds(platform, self.sata_phys)


# Timing constraints -----------------------------------------------------------------------
platform.add_platform_command("""
create_clock -name sys_clk -period 5 [get_nets sys_clk]
""")
Expand Down
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