examples: simplify CRGs using LiteX's S7PLL

enjoy-digital · Dec 2, 2019 · af86fc2 · af86fc2
1 parent 87ab241
commit af86fc2
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Showing 2 changed files with 15 additions and 50 deletions.
diff --git a/examples/targets/bist.py b/examples/targets/bist.py
@@ -4,6 +4,7 @@
 from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import SoCCore
 from litex.soc.cores.uart import UARTWishboneBridge
 
@@ -19,40 +20,15 @@ def __init__(self, platform):
         self.clock_domains.cd_sys = ClockDomain()
 
         clk200 = platform.request("clk200")
-        clk200_se = Signal()
-        self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
-
         try:
             cpu_reset = platform.request("cpu_reset")
         except:
             cpu_reset = ~platform.request("cpu_reset_n")
 
-        pll_locked = Signal()
-        pll_fb = Signal()
-        pll_sys = Signal()
-        self.specials += [
-            Instance("PLLE2_BASE",
-                p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
-
-                # VCO @ 1GHz
-                p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
-                p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
-                i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
-
-                # 200MHz
-                p_CLKOUT0_DIVIDE=5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
-
-                p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
-
-                p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, #o_CLKOUT2=,
-
-                p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
-
-                p_CLKOUT4_DIVIDE=2, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
-            ),
-            Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
-            AsyncResetSynchronizer(self.cd_sys, ~pll_locked | cpu_reset),
-        ]
+        self.submodules.pll = pll = S7PLL(speedgrade=-1)
+        self.comb += pll.reset.eq(cpu_reset)
+        pll.register_clkin(clk200, 200e6)
+        pll.create_clkout(self.cd_sys, 200e6)
 
 
 class StatusLeds(Module):

diff --git a/examples/targets/bist_nexys_video.py b/examples/targets/bist_nexys_video.py
@@ -4,6 +4,7 @@
 from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
+from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import SoCCore
 from litex.soc.cores.uart import UARTWishboneBridge
 
@@ -18,28 +19,16 @@ class CRG(Module):
     def __init__(self, platform):
         self.clock_domains.cd_sys = ClockDomain()
 
-        clk_se = platform.request("clk100")
+        clk100 = platform.request("clk100")
+        try:
+            cpu_reset = platform.request("cpu_reset")
+        except:
+            cpu_reset = ~platform.request("cpu_reset_n")
 
-        cpu_reset = ~platform.request("cpu_reset") # FIXME
-
-        pll_locked = Signal()
-        pll_fb = Signal()
-        pll_sys = Signal()
-        self.specials += [
-            Instance("PLLE2_BASE",
-                p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
-
-                # VCO @ 1GHz
-                p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
-                p_CLKFBOUT_MULT=10, p_DIVCLK_DIVIDE=1,
-                i_CLKIN1=clk_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
-
-                # 100MHz
-                p_CLKOUT0_DIVIDE=10, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys
-            ),
-            Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
-            AsyncResetSynchronizer(self.cd_sys, ~pll_locked | cpu_reset),
-        ]
+        self.submodules.pll = pll = S7PLL(speedgrade=-1)
+        self.comb += pll.reset.eq(cpu_reset)
+        pll.register_clkin(clk100, 100e6)
+        pll.create_clkout(self.cd_sys, 100e6)
 
 
 class StatusLeds(Module):