There is something strange when build, please help to check.

[adonics]

Hi Sir,

cd /home/venus/Downloads/litex-boards/litex_boards/targets
./xilinx_kc705.py --with-ethernet --with-spi-flash --with-pcie --build
then the console execute vivado synthesis and complete.
But when I enter build/xilinx_kc705/gateware
cd build/xilinx_kc705/gateware
check vivado.log
gedit vivado.log
and I find that - only several verilog (CPU,PCIe) files are read. bus, rom/ram controller, ethernet, spi etc are not be read in and synthesis. , program .bin .bit is generated.
It is strange. I attach the vivado.log here. Need your help.
BR
adonics
vivado.log